signal.tan.qmsg

通信基带信号发生器的设计

{ "Warning" "WTAN_FULL_REQUIREMENTS_NOT_MET" "Clock Setup: 'PLL:inst4\|altpll:altpll_component\|_clk0' 1729 " "Warning: Can't achieve timing requirement Clock Setup: 'PLL:inst4\|altpll:altpll_component\|_clk0' along 1729 path(s). See Report window for details." {  } {  } 0 0 "Can't achieve timing requirement %1!s! along %2!d! path(s). See Report window for details." 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "PLL:inst4\|altpll:altpll_component\|_clk1 " "Info: No valid register-to-register data paths exist for clock \"PLL:inst4\|altpll:altpll_component\|_clk1\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "CLK_IN register NCO_FM:inst31\|NCO_FM_st:NCO_FM_st_inst\|asj_nco_mob_rw:ux122\|data_out\[19\] register STATUSCONTROL:inst\|FRE7\[19\] -277 ps " "Info: Slack time is -277 ps for clock \"CLK_IN\" between source register \"NCO_FM:inst31\|NCO_FM_st:NCO_FM_st_inst\|asj_nco_mob_rw:ux122\|data_out\[19\]\" and destination register \"STATUSCONTROL:inst\|FRE7\[19\]\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "2.128 ns + Largest register register " "Info: + Largest register to register requirement is 2.128 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "1.885 ns + " "Info: + Setup relationship between source and destination is 1.885 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 5.000 ns " "Info: + Latch edge is 5.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination CLK_IN 20.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"CLK_IN\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 3.115 ns " "Info: - Launch edge is 3.115 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source PLL:inst4\|altpll:altpll_component\|_clk0 5.000 ns -1.885 ns  50 " "Info: Clock period of Source clock \"PLL:inst4\|altpll:altpll_component\|_clk0\" is 5.000 ns with  offset of -1.885 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.504 ns + Largest " "Info: + Largest clock skew is 0.504 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_IN destination 2.909 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK_IN\" to destination register is 2.909 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK_IN 1 CLK PIN_29 189 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 189; CLK Node = 'CLK_IN'" {  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK_IN } "NODE_NAME" } } { "FINAL.bdf" "" { Schematic "D:/SIGNAL_FBSJB/SIGNAL/FINAL.bdf" { { 72 -920 -752 88 "CLK_IN" "" } { 768 384 464 784 "CLK_IN" "" } { 568 384 464 584 "CLK_IN" "" } { 344 414 472 360 "CLK_IN" "" } { 16 -176 -96 32 "CLK_IN" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.729 ns) + CELL(0.711 ns) 2.909 ns STATUSCONTROL:inst\|FRE7\[19\] 2 REG LC_X21_Y9_N0 3 " "Info: 2: + IC(0.729 ns) + CELL(0.711 ns) = 2.909 ns; Loc. = LC_X21_Y9_N0; Fanout = 3; REG Node = 'STATUSCONTROL:inst\|FRE7\[19\]'" {  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.440 ns" { CLK_IN STATUSCONTROL:inst|FRE7[19] } "NODE_NAME" } } { "STATUSCONTROL.vhd" "" { Text "D:/SIGNAL_FBSJB/SIGNAL/STATUSCONTROL.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.94 % ) " "Info: Total cell delay = 2.180 ns ( 74.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.729 ns ( 25.06 % ) " "Info: Total interconnect delay = 0.729 ns ( 25.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.909 ns" { CLK_IN STATUSCONTROL:inst|FRE7[19] } "NODE_NAME" } } { "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "2.909 ns" { CLK_IN CLK_IN~out0 STATUSCONTROL:inst|FRE7[19] } { 0.000ns 0.000ns 0.729ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PLL:inst4\|altpll:altpll_component\|_clk0 source 2.405 ns - Longest register " "Info: - Longest clock path from clock \"PLL:inst4\|altpll:altpll_component\|_clk0\" to source register is 2.405 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PLL:inst4\|altpll:altpll_component\|_clk0 1 CLK PLL_1 675 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 675; CLK Node = 'PLL:inst4\|altpll:altpll_component\|_clk0'" {  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { PLL:inst4|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/eda/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.694 ns) + CELL(0.711 ns) 2.405 ns NCO_FM:inst31\|NCO_FM_st:NCO_FM_st_inst\|asj_nco_mob_rw:ux122\|data_out\[19\] 2 REG LC_X19_Y15_N2 1 " "Info: 2: + IC(1.694 ns) + CELL(0.711 ns) = 2.405 ns; Loc. = LC_X19_Y15_N2; Fanout = 1; REG Node = 'NCO_FM:inst31\|NCO_FM_st:NCO_FM_st_inst\|asj_nco_mob_rw:ux122\|data_out\[19\]'" {  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.405 ns" { PLL:inst4|altpll:altpll_component|_clk0 NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_nco_mob_rw:ux122|data_out[19] } "NODE_NAME" } } { "C:/eda/altera/megacore/nco-v2.3.1/lib/asj_nco_mob_rw.v" "" { Text "C:/eda/altera/megacore/nco-v2.3.1/lib/asj_nco_mob_rw.v" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 29.56 % ) " "Info: Total cell delay = 0.711 ns ( 29.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.694 ns ( 70.44 % ) " "Info: Total interconnect delay = 1.694 ns ( 70.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.405 ns" { PLL:inst4|altpll:altpll_component|_clk0 NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_nco_mob_rw:ux122|data_out[19] } "NODE_NAME" } } { "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "2.405 ns" { PLL:inst4|altpll:altpll_component|_clk0 NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_nco_mob_rw:ux122|data_out[19] } { 0.000ns 1.694ns } { 0.000ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.909 ns" { CLK_IN STATUSCONTROL:inst|FRE7[19] } "NODE_NAME" } } { "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "2.909 ns" { CLK_IN CLK_IN~out0 STATUSCONTROL:inst|FRE7[19] } { 0.000ns 0.000ns 0.729ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.405 ns" { PLL:inst4|altpll:altpll_component|_clk0 NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_nco_mob_rw:ux122|data_out[19] } "NODE_NAME" } } { "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "2.405 ns" { PLL:inst4|altpll:altpll_component|_clk0 NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_nco_mob_rw:ux122|data_out[19] } { 0.000ns 1.694ns } { 0.000ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "C:/eda/altera/megacore/nco-v2.3.1/lib/asj_nco_mob_rw.v" "" { Text "C:/eda/altera/megacore/nco-v2.3.1/lib/asj_nco_mob_rw.v" 36 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" {  } { { "STATUSCONTROL.vhd" "" { Text "D:/SIGNAL_FBSJB/SIGNAL/STATUSCONTROL.vhd" 32 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.909 ns" { CLK_IN STATUSCONTROL:inst|FRE7[19] } "NODE_NAME" } } { "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "2.909 ns" { CLK_IN CLK_IN~out0 STATUSCONTROL:inst|FRE7[19] } { 0.000ns 0.000ns 0.729ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.405 ns" { PLL:inst4|altpll:altpll_component|_clk0 NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_nco_mob_rw:ux122|data_out[19] } "NODE_NAME" } } { "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "2.405 ns" { PLL:inst4|altpll:altpll_component|_clk0 NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_nco_mob_rw:ux122|data_out[19] } { 0.000ns 1.694ns } { 0.000ns 0.711ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.405 ns - Longest register register " "Info: - Longest register to register delay is 2.405 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns NCO_FM:inst31\|NCO_FM_st:NCO_FM_st_inst\|asj_nco_mob_rw:ux122\|data_out\[19\] 1 REG LC_X19_Y15_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X19_Y15_N2; Fanout = 1; REG Node = 'NCO_FM:inst31\|NCO_FM_st:NCO_FM_st_inst\|asj_nco_mob_rw:ux122\|data_out\[19\]'" {  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_nco_mob_rw:ux122|data_out[19] } "NODE_NAME" } } { "C:/eda/altera/megacore/nco-v2.3.1/lib/asj_nco_mob_rw.v" "" { Text "C:/eda/altera/megacore/nco-v2.3.1/lib/asj_nco_mob_rw.v" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.096 ns) + CELL(0.309 ns) 2.405 ns STATUSCONTROL:inst\|FRE7\[19\] 2 REG LC_X21_Y9_N0 3 " "Info: 2: + IC(2.096 ns) + CELL(0.309 ns) = 2.405 ns; Loc. = LC_X21_Y9_N0; Fanout = 3; REG Node = 'STATUSCONTROL:inst\|FRE7\[19\]'" {  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.405 ns" { NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_nco_mob_rw:ux122|data_out[19] STATUSCONTROL:inst|FRE7[19] } "NODE_NAME" } } { "STATUSCONTROL.vhd" "" { Text "D:/SIGNAL_FBSJB/SIGNAL/STATUSCONTROL.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns ( 12.85 % ) " "Info: Total cell delay = 0.309 ns ( 12.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.096 ns ( 87.15 % ) " "Info: Total interconnect delay = 2.096 ns ( 87.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.405 ns" { NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_nco_mob_rw:ux122|data_out[19] STATUSCONTROL:inst|FRE7[19] } "NODE_NAME" } } { "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "2.405 ns" { NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_nco_mob_rw:ux122|data_out[19] STATUSCONTROL:inst|FRE7[19] } { 0.000ns 2.096ns } { 0.000ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.909 ns" { CLK_IN STATUSCONTROL:inst|FRE7[19] } "NODE_NAME" } } { "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "2.909 ns" { CLK_IN CLK_IN~out0 STATUSCONTROL:inst|FRE7[19] } { 0.000ns 0.000ns 0.729ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.405 ns" { PLL:inst4|altpll:altpll_component|_clk0 NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_nco_mob_rw:ux122|data_out[19] } "NODE_NAME" } } { "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "2.405 ns" { PLL:inst4|altpll:altpll_component|_clk0 NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_nco_mob_rw:ux122|data_out[19] } { 0.000ns 1.694ns } { 0.000ns 0.711ns } } } { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.405 ns" { NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_nco_mob_rw:ux122|data_out[19] STATUSCONTROL:inst|FRE7[19] } "NODE_NAME" } } { "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "2.405 ns" { NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_nco_mob_rw:ux122|data_out[19] STATUSCONTROL:inst|FRE7[19] } { 0.000ns 2.096ns } { 0.000ns 0.309ns } } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Warning" "WTAN_FULL_REQUIREMENTS_NOT_MET" "Clock Setup: 'CLK_IN' 7 " "Warning: Can't achieve timing requirement Clock Setup: 'CLK_IN' along 7 path(s). See Report window for details." {  } {  } 0 0 "Can't achieve timing requirement %1!s! along %2!d! path(s). See Report window for details." 0 0}