signal.tan.qmsg

通信基带信号发生器的设计

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "EN " "Info: Assuming node \"EN\" is an undefined clock" {  } { { "FINAL.bdf" "" { Schematic "D:/SIGNAL_FBSJB/SIGNAL/FINAL.bdf" { { 432 -920 -752 448 "EN" "" } } } } { "c:/eda/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/eda/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "EN" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "TXD " "Info: Assuming node \"TXD\" is an undefined clock" {  } { { "FINAL.bdf" "" { Schematic "D:/SIGNAL_FBSJB/SIGNAL/FINAL.bdf" { { 448 -920 -752 464 "TXD" "" } } } } { "c:/eda/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/eda/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "TXD" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "4 " "Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "FREQUENCY_DIV:inst8\|CLK_OUT " "Info: Detected ripple clock \"FREQUENCY_DIV:inst8\|CLK_OUT\" as buffer" {  } { { "FREQUENCY_DIV.vhd" "" { Text "D:/SIGNAL_FBSJB/SIGNAL/FREQUENCY_DIV.vhd" 7 -1 0 } } { "c:/eda/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/eda/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "FREQUENCY_DIV:inst8\|CLK_OUT" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "FREQUENCY_DIV:inst10\|CLK_OUT " "Info: Detected ripple clock \"FREQUENCY_DIV:inst10\|CLK_OUT\" as buffer" {  } { { "FREQUENCY_DIV.vhd" "" { Text "D:/SIGNAL_FBSJB/SIGNAL/FREQUENCY_DIV.vhd" 7 -1 0 } } { "c:/eda/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/eda/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "FREQUENCY_DIV:inst10\|CLK_OUT" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "FREQUENCY_DIV:inst9\|CLK_OUT " "Info: Detected ripple clock \"FREQUENCY_DIV:inst9\|CLK_OUT\" as buffer" {  } { { "FREQUENCY_DIV.vhd" "" { Text "D:/SIGNAL_FBSJB/SIGNAL/FREQUENCY_DIV.vhd" 7 -1 0 } } { "c:/eda/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/eda/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "FREQUENCY_DIV:inst9\|CLK_OUT" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fangbo:inst23\|clr " "Info: Detected ripple clock \"fangbo:inst23\|clr\" as buffer" {  } { { "fangbo.vhd" "" { Text "D:/SIGNAL_FBSJB/SIGNAL/fangbo.vhd" 15 -1 0 } } { "c:/eda/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/eda/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "fangbo:inst23\|clr" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0 0 "Found timing assignments -- calculating delays" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "PLL:inst4\|altpll:altpll_component\|_clk0 register STATUSCONTROL:inst\|EN_FM memory NCO_FM:inst31\|NCO_FM_st:NCO_FM_st_inst\|asj_nco_as_m_cen:ux0120\|altsyncram:altsyncram_component0\|altsyncram_kq81:auto_generated\|ram_block1a22~porta_address_reg9 -1.095 ns " "Info: Slack time is -1.095 ns for clock \"PLL:inst4\|altpll:altpll_component\|_clk0\" between source register \"STATUSCONTROL:inst\|EN_FM\" and destination memory \"NCO_FM:inst31\|NCO_FM_st:NCO_FM_st_inst\|asj_nco_as_m_cen:ux0120\|altsyncram:altsyncram_component0\|altsyncram_kq81:auto_generated\|ram_block1a22~porta_address_reg9\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "2.312 ns + Largest register memory " "Info: + Largest register to memory requirement is 2.312 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "3.115 ns + " "Info: + Setup relationship between source and destination is 3.115 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 3.115 ns " "Info: + Latch edge is 3.115 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination PLL:inst4\|altpll:altpll_component\|_clk0 5.000 ns -1.885 ns  50 " "Info: Clock period of Destination clock \"PLL:inst4\|altpll:altpll_component\|_clk0\" is 5.000 ns with  offset of -1.885 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source CLK_IN 20.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"CLK_IN\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.486 ns + Largest " "Info: + Largest clock skew is -0.486 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PLL:inst4\|altpll:altpll_component\|_clk0 destination 2.416 ns + Shortest memory " "Info: + Shortest clock path from clock \"PLL:inst4\|altpll:altpll_component\|_clk0\" to destination memory is 2.416 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PLL:inst4\|altpll:altpll_component\|_clk0 1 CLK PLL_1 675 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 675; CLK Node = 'PLL:inst4\|altpll:altpll_component\|_clk0'" {  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { PLL:inst4|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/eda/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.694 ns) + CELL(0.722 ns) 2.416 ns NCO_FM:inst31\|NCO_FM_st:NCO_FM_st_inst\|asj_nco_as_m_cen:ux0120\|altsyncram:altsyncram_component0\|altsyncram_kq81:auto_generated\|ram_block1a22~porta_address_reg9 2 MEM M4K_X17_Y14 4 " "Info: 2: + IC(1.694 ns) + CELL(0.722 ns) = 2.416 ns; Loc. = M4K_X17_Y14; Fanout = 4; MEM Node = 'NCO_FM:inst31\|NCO_FM_st:NCO_FM_st_inst\|asj_nco_as_m_cen:ux0120\|altsyncram:altsyncram_component0\|altsyncram_kq81:auto_generated\|ram_block1a22~porta_address_reg9'" {  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.416 ns" { PLL:inst4|altpll:altpll_component|_clk0 NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_kq81:auto_generated|ram_block1a22~porta_address_reg9 } "NODE_NAME" } } { "db/altsyncram_kq81.tdf" "" { Text "D:/SIGNAL_FBSJB/SIGNAL/db/altsyncram_kq81.tdf" 484 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.722 ns ( 29.88 % ) " "Info: Total cell delay = 0.722 ns ( 29.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.694 ns ( 70.12 % ) " "Info: Total interconnect delay = 1.694 ns ( 70.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.416 ns" { PLL:inst4|altpll:altpll_component|_clk0 NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_kq81:auto_generated|ram_block1a22~porta_address_reg9 } "NODE_NAME" } } { "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "2.416 ns" { PLL:inst4|altpll:altpll_component|_clk0 NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_kq81:auto_generated|ram_block1a22~porta_address_reg9 } { 0.000ns 1.694ns } { 0.000ns 0.722ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_IN source 2.902 ns - Longest register " "Info: - Longest clock path from clock \"CLK_IN\" to source register is 2.902 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK_IN 1 CLK PIN_29 189 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 189; CLK Node = 'CLK_IN'" {  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK_IN } "NODE_NAME" } } { "FINAL.bdf" "" { Schematic "D:/SIGNAL_FBSJB/SIGNAL/FINAL.bdf" { { 72 -920 -752 88 "CLK_IN" "" } { 768 384 464 784 "CLK_IN" "" } { 568 384 464 584 "CLK_IN" "" } { 344 414 472 360 "CLK_IN" "" } { 16 -176 -96 32 "CLK_IN" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.722 ns) + CELL(0.711 ns) 2.902 ns STATUSCONTROL:inst\|EN_FM 2 REG LC_X16_Y9_N6 221 " "Info: 2: + IC(0.722 ns) + CELL(0.711 ns) = 2.902 ns; Loc. = LC_X16_Y9_N6; Fanout = 221; REG Node = 'STATUSCONTROL:inst\|EN_FM'" {  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.433 ns" { CLK_IN STATUSCONTROL:inst|EN_FM } "NODE_NAME" } } { "STATUSCONTROL.vhd" "" { Text "D:/SIGNAL_FBSJB/SIGNAL/STATUSCONTROL.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 75.12 % ) " "Info: Total cell delay = 2.180 ns ( 75.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.722 ns ( 24.88 % ) " "Info: Total interconnect delay = 0.722 ns ( 24.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.902 ns" { CLK_IN STATUSCONTROL:inst|EN_FM } "NODE_NAME" } } { "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "2.902 ns" { CLK_IN CLK_IN~out0 STATUSCONTROL:inst|EN_FM } { 0.000ns 0.000ns 0.722ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.416 ns" { PLL:inst4|altpll:altpll_component|_clk0 NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_kq81:auto_generated|ram_block1a22~porta_address_reg9 } "NODE_NAME" } } { "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "2.416 ns" { PLL:inst4|altpll:altpll_component|_clk0 NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_kq81:auto_generated|ram_block1a22~porta_address_reg9 } { 0.000ns 1.694ns } { 0.000ns 0.722ns } } } { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.902 ns" { CLK_IN STATUSCONTROL:inst|EN_FM } "NODE_NAME" } } { "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "2.902 ns" { CLK_IN CLK_IN~out0 STATUSCONTROL:inst|EN_FM } { 0.000ns 0.000ns 0.722ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "STATUSCONTROL.vhd" "" { Text "D:/SIGNAL_FBSJB/SIGNAL/STATUSCONTROL.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns - " "Info: - Micro setup delay of destination is 0.093 ns" {  } { { "db/altsyncram_kq81.tdf" "" { Text "D:/SIGNAL_FBSJB/SIGNAL/db/altsyncram_kq81.tdf" 484 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.416 ns" { PLL:inst4|altpll:altpll_component|_clk0 NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_kq81:auto_generated|ram_block1a22~porta_address_reg9 } "NODE_NAME" } } { "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "2.416 ns" { PLL:inst4|altpll:altpll_component|_clk0 NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_kq81:auto_generated|ram_block1a22~porta_address_reg9 } { 0.000ns 1.694ns } { 0.000ns 0.722ns } } } { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.902 ns" { CLK_IN STATUSCONTROL:inst|EN_FM } "NODE_NAME" } } { "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "2.902 ns" { CLK_IN CLK_IN~out0 STATUSCONTROL:inst|EN_FM } { 0.000ns 0.000ns 0.722ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.407 ns - Longest register memory " "Info: - Longest register to memory delay is 3.407 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns STATUSCONTROL:inst\|EN_FM 1 REG LC_X16_Y9_N6 221 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y9_N6; Fanout = 221; REG Node = 'STATUSCONTROL:inst\|EN_FM'" {  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { STATUSCONTROL:inst|EN_FM } "NODE_NAME" } } { "STATUSCONTROL.vhd" "" { Text "D:/SIGNAL_FBSJB/SIGNAL/STATUSCONTROL.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.442 ns) + CELL(0.965 ns) 3.407 ns NCO_FM:inst31\|NCO_FM_st:NCO_FM_st_inst\|asj_nco_as_m_cen:ux0120\|altsyncram:altsyncram_component0\|altsyncram_kq81:auto_generated\|ram_block1a22~porta_address_reg9 2 MEM M4K_X17_Y14 4 " "Info: 2: + IC(2.442 ns) + CELL(0.965 ns) = 3.407 ns; Loc. = M4K_X17_Y14; Fanout = 4; MEM Node = 'NCO_FM:inst31\|NCO_FM_st:NCO_FM_st_inst\|asj_nco_as_m_cen:ux0120\|altsyncram:altsyncram_component0\|altsyncram_kq81:auto_generated\|ram_block1a22~porta_address_reg9'" {  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.407 ns" { STATUSCONTROL:inst|EN_FM NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_kq81:auto_generated|ram_block1a22~porta_address_reg9 } "NODE_NAME" } } { "db/altsyncram_kq81.tdf" "" { Text "D:/SIGNAL_FBSJB/SIGNAL/db/altsyncram_kq81.tdf" 484 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.965 ns ( 28.32 % ) " "Info: Total cell delay = 0.965 ns ( 28.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.442 ns ( 71.68 % ) " "Info: Total interconnect delay = 2.442 ns ( 71.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.407 ns" { STATUSCONTROL:inst|EN_FM NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_kq81:auto_generated|ram_block1a22~porta_address_reg9 } "NODE_NAME" } } { "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "3.407 ns" { STATUSCONTROL:inst|EN_FM NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_kq81:auto_generated|ram_block1a22~porta_address_reg9 } { 0.000ns 2.442ns } { 0.000ns 0.965ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.416 ns" { PLL:inst4|altpll:altpll_component|_clk0 NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_kq81:auto_generated|ram_block1a22~porta_address_reg9 } "NODE_NAME" } } { "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "2.416 ns" { PLL:inst4|altpll:altpll_component|_clk0 NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_kq81:auto_generated|ram_block1a22~porta_address_reg9 } { 0.000ns 1.694ns } { 0.000ns 0.722ns } } } { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.902 ns" { CLK_IN STATUSCONTROL:inst|EN_FM } "NODE_NAME" } } { "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "2.902 ns" { CLK_IN CLK_IN~out0 STATUSCONTROL:inst|EN_FM } { 0.000ns 0.000ns 0.722ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.407 ns" { STATUSCONTROL:inst|EN_FM NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_kq81:auto_generated|ram_block1a22~porta_address_reg9 } "NODE_NAME" } } { "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/eda/altera/quartus60/win/Technology_Viewer.qrui" "3.407 ns" { STATUSCONTROL:inst|EN_FM NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_kq81:auto_generated|ram_block1a22~porta_address_reg9 } { 0.000ns 2.442ns } { 0.000ns 0.965ns } } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}