signal.fit.qmsg

通信基带信号发生器的设计

{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "TXD " "Info: Pin \"TXD\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "FINAL.bdf" "" { Schematic "D:/SIGNAL_FBSJB/SIGNAL/FINAL.bdf" { { 448 -920 -752 464 "TXD" "" } } } } { "c:/eda/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/eda/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "TXD" } } } } { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { TXD } "NODE_NAME" } } { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { TXD } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "FREQUENCY_DIV:inst10\|CLK_OUT Global clock " "Info: Automatically promoted some destinations of signal \"FREQUENCY_DIV:inst10\|CLK_OUT\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FREQUENCY_DIV:inst10\|CLK_OUT " "Info: Destination \"FREQUENCY_DIV:inst10\|CLK_OUT\" may be non-global or may not use global clock" {  } { { "FREQUENCY_DIV.vhd" "" { Text "D:/SIGNAL_FBSJB/SIGNAL/FREQUENCY_DIV.vhd" 7 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FREQUENCY_DIV:inst10\|CLK_OUT~91 " "Info: Destination \"FREQUENCY_DIV:inst10\|CLK_OUT~91\" may be non-global or may not use global clock" {  } { { "FREQUENCY_DIV.vhd" "" { Text "D:/SIGNAL_FBSJB/SIGNAL/FREQUENCY_DIV.vhd" 7 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "FREQUENCY_DIV.vhd" "" { Text "D:/SIGNAL_FBSJB/SIGNAL/FREQUENCY_DIV.vhd" 7 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "FREQUENCY_DIV:inst8\|CLK_OUT Global clock " "Info: Automatically promoted some destinations of signal \"FREQUENCY_DIV:inst8\|CLK_OUT\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FREQUENCY_DIV:inst8\|CLK_OUT " "Info: Destination \"FREQUENCY_DIV:inst8\|CLK_OUT\" may be non-global or may not use global clock" {  } { { "FREQUENCY_DIV.vhd" "" { Text "D:/SIGNAL_FBSJB/SIGNAL/FREQUENCY_DIV.vhd" 7 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FREQUENCY_DIV:inst8\|CLK_OUT~91 " "Info: Destination \"FREQUENCY_DIV:inst8\|CLK_OUT~91\" may be non-global or may not use global clock" {  } { { "FREQUENCY_DIV.vhd" "" { Text "D:/SIGNAL_FBSJB/SIGNAL/FREQUENCY_DIV.vhd" 7 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "FREQUENCY_DIV.vhd" "" { Text "D:/SIGNAL_FBSJB/SIGNAL/FREQUENCY_DIV.vhd" 7 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "FREQUENCY_DIV:inst9\|CLK_OUT Global clock " "Info: Automatically promoted some destinations of signal \"FREQUENCY_DIV:inst9\|CLK_OUT\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FREQUENCY_DIV:inst9\|CLK_OUT " "Info: Destination \"FREQUENCY_DIV:inst9\|CLK_OUT\" may be non-global or may not use global clock" {  } { { "FREQUENCY_DIV.vhd" "" { Text "D:/SIGNAL_FBSJB/SIGNAL/FREQUENCY_DIV.vhd" 7 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FREQUENCY_DIV:inst9\|CLK_OUT~93 " "Info: Destination \"FREQUENCY_DIV:inst9\|CLK_OUT~93\" may be non-global or may not use global clock" {  } { { "FREQUENCY_DIV.vhd" "" { Text "D:/SIGNAL_FBSJB/SIGNAL/FREQUENCY_DIV.vhd" 7 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "FREQUENCY_DIV.vhd" "" { Text "D:/SIGNAL_FBSJB/SIGNAL/FREQUENCY_DIV.vhd" 7 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0}
{ "Extra Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" 1 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:01 " "Info: Finished register packing: elapsed time is 00:00:01" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Warning" "WCUT_CUT_YGR_PLL_BAD_FANOUT_CLK3" "clk1 PLL:inst4\|altpll:altpll_component\|pll " "Warning: Output port clk1 of PLL \"PLL:inst4\|altpll:altpll_component\|pll\" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" {  } { { "altpll.tdf" "" { Text "c:/eda/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } } { "PLL.vhd" "" { Text "D:/SIGNAL_FBSJB/SIGNAL/PLL.vhd" 135 -1 0 } } { "FINAL.bdf" "" { Schematic "D:/SIGNAL_FBSJB/SIGNAL/FINAL.bdf" { { 16 -672 -432 192 "inst4" "" } } } }  } 0 0 "Output port %1!s! of PLL \"%2!s!\" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:05 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:05" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}