signal.fit.qmsg

通信基带信号发生器的设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version " "Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 15 10:52:51 2002 " "Info: Processing started: Tue Oct 15 10:52:51 2002" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off SIGNAL -c SIGNAL " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off SIGNAL -c SIGNAL" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "SIGNAL EP1C6Q240C8 " "Info: Selected device EP1C6Q240C8 for design \"SIGNAL\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "ICUT_CUT_YGR_PLL_CAN_ACHIEVE_RATIO_AND_PHASE_SHIFT" "PLL:inst4\|altpll:altpll_component\|pll " "Info: Implementing parameter values for PLL \"PLL:inst4\|altpll:altpll_component\|pll\"" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "PLL:inst4\|altpll:altpll_component\|_clk0 4 1 0 0 " "Info: Implementing clock multiplication of 4, clock division of 1, and phase shift of 0 degrees (0 ps) for PLL:inst4\|altpll:altpll_component\|_clk0 port" {  } {  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "PLL:inst4\|altpll:altpll_component\|_clk1 2 1 0 0 " "Info: Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for PLL:inst4\|altpll:altpll_component\|_clk1 port" {  } {  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0}  } { { "altpll.tdf" "" { Text "c:/eda/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } } { "PLL.vhd" "" { Text "D:/SIGNAL_FBSJB/SIGNAL/PLL.vhd" 135 -1 0 } } { "FINAL.bdf" "" { Schematic "D:/SIGNAL_FBSJB/SIGNAL/FINAL.bdf" { { 16 -672 -432 192 "inst4" "" } } } }  } 0 0 "Implementing parameter values for PLL \"%1!s!\"" 0 0}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" {  } {  } 0 0 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C12Q240C8 " "Info: Device EP1C12Q240C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "ITAN_TDC_USER_OPTIMIZATION_GOALS" "" "Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 0 "Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" 0 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0}
{ "Info" "IFYGR_FYGR_PLL_CLK_PROMOTION" "" "Info: Promoted PLL clock signals" { { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK" "CLK_IN " "Info: Promoted signal \"CLK_IN\" to use global clock" {  } { { "c:/eda/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/eda/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "CLK_IN" } { 0 "CLK_IN" } } } } { "FINAL.bdf" "" { Schematic "D:/SIGNAL_FBSJB/SIGNAL/FINAL.bdf" { { 72 -920 -752 88 "CLK_IN" "" } { 768 384 464 784 "CLK_IN" "" } { 568 384 464 584 "CLK_IN" "" } { 344 414 472 360 "CLK_IN" "" } { 16 -176 -96 32 "CLK_IN" "" } } } } { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK_IN } "NODE_NAME" } } { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK_IN } "NODE_NAME" } }  } 0 0 "Promoted signal \"%1!s!\" to use global clock" 0 0} { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK_USER" "PLL:inst4\|altpll:altpll_component\|_clk0 " "Info: Promoted signal \"PLL:inst4\|altpll:altpll_component\|_clk0\" to use global clock (user assigned)" {  } { { "c:/eda/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/eda/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PLL:inst4\|altpll:altpll_component\|_clk0" } { 0 "PLL:inst4\|altpll:altpll_component\|_clk0" } } } } { "FINAL.bdf" "" { Schematic "D:/SIGNAL_FBSJB/SIGNAL/FINAL.bdf" { { 16 -672 -432 192 "inst4" "" } } } } { "altpll.tdf" "" { Text "c:/eda/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } } { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { PLL:inst4|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { PLL:inst4|altpll:altpll_component|_clk0 } "NODE_NAME" } }  } 0 0 "Promoted signal \"%1!s!\" to use global clock (user assigned)" 0 0} { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK_USER" "PLL:inst4\|altpll:altpll_component\|_clk1 " "Info: Promoted signal \"PLL:inst4\|altpll:altpll_component\|_clk1\" to use global clock (user assigned)" {  } { { "c:/eda/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/eda/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PLL:inst4\|altpll:altpll_component\|_clk1" } { 0 "PLL:inst4\|altpll:altpll_component\|_clk0" } } } } { "FINAL.bdf" "" { Schematic "D:/SIGNAL_FBSJB/SIGNAL/FINAL.bdf" { { 16 -672 -432 192 "inst4" "" } } } } { "altpll.tdf" "" { Text "c:/eda/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } } { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { PLL:inst4|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { PLL:inst4|altpll:altpll_component|_clk0 } "NODE_NAME" } }  } 0 0 "Promoted signal \"%1!s!\" to use global clock (user assigned)" 0 0}  } {  } 0 0 "Promoted PLL clock signals" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "PLL Placement Operation " "Info: Completed PLL Placement Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "EN Global clock " "Info: Automatically promoted some destinations of signal \"EN\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PARALLEL:inst6\|TEMP1\[0\] " "Info: Destination \"PARALLEL:inst6\|TEMP1\[0\]\" may be non-global or may not use global clock" {  } { { "PARALLEL.vhd" "" { Text "D:/SIGNAL_FBSJB/SIGNAL/PARALLEL.vhd" 23 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PARALLEL:inst6\|TEMP0\[0\] " "Info: Destination \"PARALLEL:inst6\|TEMP0\[0\]\" may be non-global or may not use global clock" {  } { { "PARALLEL.vhd" "" { Text "D:/SIGNAL_FBSJB/SIGNAL/PARALLEL.vhd" 23 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PARALLEL:inst6\|TEMP0\[1\] " "Info: Destination \"PARALLEL:inst6\|TEMP0\[1\]\" may be non-global or may not use global clock" {  } { { "PARALLEL.vhd" "" { Text "D:/SIGNAL_FBSJB/SIGNAL/PARALLEL.vhd" 23 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PARALLEL:inst6\|TEMP0\[2\] " "Info: Destination \"PARALLEL:inst6\|TEMP0\[2\]\" may be non-global or may not use global clock" {  } { { "PARALLEL.vhd" "" { Text "D:/SIGNAL_FBSJB/SIGNAL/PARALLEL.vhd" 23 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PARALLEL:inst6\|TEMP0\[3\] " "Info: Destination \"PARALLEL:inst6\|TEMP0\[3\]\" may be non-global or may not use global clock" {  } { { "PARALLEL.vhd" "" { Text "D:/SIGNAL_FBSJB/SIGNAL/PARALLEL.vhd" 23 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PARALLEL:inst6\|TEMP0\[4\] " "Info: Destination \"PARALLEL:inst6\|TEMP0\[4\]\" may be non-global or may not use global clock" {  } { { "PARALLEL.vhd" "" { Text "D:/SIGNAL_FBSJB/SIGNAL/PARALLEL.vhd" 23 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PARALLEL:inst6\|TEMP0\[5\] " "Info: Destination \"PARALLEL:inst6\|TEMP0\[5\]\" may be non-global or may not use global clock" {  } { { "PARALLEL.vhd" "" { Text "D:/SIGNAL_FBSJB/SIGNAL/PARALLEL.vhd" 23 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PARALLEL:inst6\|TEMP0\[6\] " "Info: Destination \"PARALLEL:inst6\|TEMP0\[6\]\" may be non-global or may not use global clock" {  } { { "PARALLEL.vhd" "" { Text "D:/SIGNAL_FBSJB/SIGNAL/PARALLEL.vhd" 23 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PARALLEL:inst6\|TEMP0\[7\] " "Info: Destination \"PARALLEL:inst6\|TEMP0\[7\]\" may be non-global or may not use global clock" {  } { { "PARALLEL.vhd" "" { Text "D:/SIGNAL_FBSJB/SIGNAL/PARALLEL.vhd" 23 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PARALLEL:inst6\|TEMP1\[1\] " "Info: Destination \"PARALLEL:inst6\|TEMP1\[1\]\" may be non-global or may not use global clock" {  } { { "PARALLEL.vhd" "" { Text "D:/SIGNAL_FBSJB/SIGNAL/PARALLEL.vhd" 23 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_LIMITED_TO_SUB" "10 " "Info: Limited to 10 non-global destinations" {  } {  } 0 0 "Limited to %1!d! non-global destinations" 0 0}  } { { "FINAL.bdf" "" { Schematic "D:/SIGNAL_FBSJB/SIGNAL/FINAL.bdf" { { 432 -920 -752 448 "EN" "" } } } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "EN " "Info: Pin \"EN\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "FINAL.bdf" "" { Schematic "D:/SIGNAL_FBSJB/SIGNAL/FINAL.bdf" { { 432 -920 -752 448 "EN" "" } } } } { "c:/eda/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/eda/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "EN" } } } } { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { EN } "NODE_NAME" } } { "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/eda/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { EN } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "TXD Global clock " "Info: Automatically promoted signal \"TXD\" to use Global clock" {  } { { "FINAL.bdf" "" { Schematic "D:/SIGNAL_FBSJB/SIGNAL/FINAL.bdf" { { 448 -920 -752 464 "TXD" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}