📄 alt_u_div_uqe.tdf
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--alt_u_div DEVICE_FAMILY="Cyclone" LPM_PIPELINE=0 MAXIMIZE_SPEED=5 SKIP_BITS=0 WIDTH_D=2 WIDTH_N=24 WIDTH_Q=24 WIDTH_R=2 denominator numerator quotient remainder
--VERSION_BEGIN 6.0 cbx_cycloneii 2006:02:07:15:19:20:SJ cbx_lpm_abs 2006:01:02:19:20:00:SJ cbx_lpm_add_sub 2006:01:09:11:17:20:SJ cbx_lpm_divide 2006:01:18:17:01:10:SJ cbx_mgl 2006:05:17:10:06:16:SJ cbx_stratix 2006:05:17:09:28:32:SJ cbx_stratixii 2006:03:03:09:35:36:SJ cbx_util_mgl 2006:01:09:10:46:36:SJ VERSION_END
-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
FUNCTION add_sub_3dc (dataa[0..0], datab[0..0])
RETURNS ( cout, result[0..0]);
FUNCTION add_sub_4dc (dataa[1..0], datab[1..0])
RETURNS ( cout, result[1..0]);
FUNCTION add_sub_5dc (dataa[2..0], datab[2..0])
RETURNS ( cout, result[2..0]);
--synthesis_resources = lut 3
SUBDESIGN alt_u_div_uqe
(
den_out[1..0] : output;
denominator[1..0] : input;
numerator[23..0] : input;
quotient[23..0] : output;
remainder[1..0] : output;
)
VARIABLE
add_sub_0 : add_sub_3dc;
add_sub_1 : add_sub_4dc;
add_sub_10 : add_sub_5dc;
add_sub_11 : add_sub_5dc;
add_sub_12 : add_sub_5dc;
add_sub_13 : add_sub_5dc;
add_sub_14 : add_sub_5dc;
add_sub_15 : add_sub_5dc;
add_sub_16 : add_sub_5dc;
add_sub_17 : add_sub_5dc;
add_sub_18 : add_sub_5dc;
add_sub_19 : add_sub_5dc;
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