decode_nga.tdf

通信基带信号发生器的设计

--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone" LPM_DECODES=8 LPM_WIDTH=3 data enable eq
--VERSION_BEGIN 6.0 cbx_cycloneii 2006:02:07:15:19:20:SJ cbx_lpm_add_sub 2006:01:09:11:17:20:SJ cbx_lpm_compare 2006:01:09:11:15:40:SJ cbx_lpm_decode 2006:01:09:11:16:44:SJ cbx_mgl 2006:04:14:11:14:36:SJ cbx_stratix 2006:02:07:15:17:04:SJ cbx_stratixii 2006:03:03:09:35:36:SJ  VERSION_END


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--synthesis_resources = lut 8 
SUBDESIGN decode_nga
( 
	data[2..0]	:	input;
	enable	:	input;
	eq[7..0]	:	output;
) 
VARIABLE 
	data_wire[2..0]	: WIRE;
	enable_wire	: WIRE;
	eq_node[7..0]	: WIRE;
	eq_wire[7..0]	: WIRE;
	w_anode3354w[3..0]	: WIRE;
	w_anode3371w[3..0]	: WIRE;
	w_anode3381w[3..0]	: WIRE;
	w_anode3391w[3..0]	: WIRE;
	w_anode3401w[3..0]	: WIRE;
	w_anode3411w[3..0]	: WIRE;
	w_anode3421w[3..0]	: WIRE;
	w_anode3431w[3..0]	: WIRE;

BEGIN 
	data_wire[] = data[];
	enable_wire = enable;
	eq[] = eq_node[];
	eq_node[7..0] = eq_wire[7..0];
	eq_wire[] = ( w_anode3431w[3..3], w_anode3421w[3..3], w_anode3411w[3..3], w_anode3401w[3..3], w_anode3391w[3..3], w_anode3381w[3..3], w_anode3371w[3..3], w_anode3354w[3..3]);
	w_anode3354w[] = ( (w_anode3354w[2..2] & (! data_wire[2..2])), (w_anode3354w[1..1] & (! data_wire[1..1])), (w_anode3354w[0..0] & (! data_wire[0..0])), enable_wire);
	w_anode3371w[] = ( (w_anode3371w[2..2] & (! data_wire[2..2])), (w_anode3371w[1..1] & (! data_wire[1..1])), (w_anode3371w[0..0] & data_wire[0..0]), enable_wire);
	w_anode3381w[] = ( (w_anode3381w[2..2] & (! data_wire[2..2])), (w_anode3381w[1..1] & data_wire[1..1]), (w_anode3381w[0..0] & (! data_wire[0..0])), enable_wire);
	w_anode3391w[] = ( (w_anode3391w[2..2] & (! data_wire[2..2])), (w_anode3391w[1..1] & data_wire[1..1]), (w_anode3391w[0..0] & data_wire[0..0]), enable_wire);
	w_anode3401w[] = ( (w_anode3401w[2..2] & data_wire[2..2]), (w_anode3401w[1..1] & (! data_wire[1..1])), (w_anode3401w[0..0] & (! data_wire[0..0])), enable_wire);
	w_anode3411w[] = ( (w_anode3411w[2..2] & data_wire[2..2]), (w_anode3411w[1..1] & (! data_wire[1..1])), (w_anode3411w[0..0] & data_wire[0..0]), enable_wire);
	w_anode3421w[] = ( (w_anode3421w[2..2] & data_wire[2..2]), (w_anode3421w[1..1] & data_wire[1..1]), (w_anode3421w[0..0] & (! data_wire[0..0])), enable_wire);
	w_anode3431w[] = ( (w_anode3431w[2..2] & data_wire[2..2]), (w_anode3431w[1..1] & data_wire[1..1]), (w_anode3431w[0..0] & data_wire[0..0]), enable_wire);
END;
--VALID FILE