fangbo.vhd

来自「通信基带信号发生器的设计」· VHDL 代码 · 共 58 行

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_arith.all; 
use ieee.std_logic_unsigned.all; 
entity fangbo is 
port( 
	en,clk : in std_logic; 
	co : out std_logic_vector(9 downto 0)
	); 
end; 

architecture dacc of fangbo is 
signal q: integer range 1 downto 0; 
signal count: integer range 999 downto 0:=0; 
signal clr:std_logic; 
begin 

process(clk)
begin
if en='1' then 
	if clk'event and clk='1' then
		if count=999 then 
			count<=0;
		else 
			count<=count+1;
		end if;
	end if;
end if;	
end process;

process(clk)
begin
	if clk'event and clk='1' then
		if count=500 then 
			clr<='1';
		elsif  count=0 then 
			clr<='0';
		end if;
	end if;
end process;


process(clr) 
begin 
	if clr'event and clr='1' then 
		q<=q+1; 
	end if; 
end process; 

process(q) 
begin 
	case q is 
		when 0=>co<="1111111111"; 
		when 1=>co<="0000000000"; 
		when others=>null; 
	end case; 
end process; 
end architecture;