xulie.vhd

通信基带信号发生器的设计

library ieee;
use ieee.std_logic_1164.all;

entity xulie is
port(clk:in std_logic;
	qout:out std_logic);
end xulie;

architecture xlcs of xulie is
component dff
port(d,clk:in std_logic;
	q:out std_logic);
end component;
signal i1,i2,i3:std_logic;
begin
u1:dff port map(d=>((not(i2))and(not(i3))),clk=>clk,q=>i1);
u2:dff port map(d=>i1,clk=>clk,q=>i2);
u3:dff port map(d=>i2,clk=>clk,q=>i3);
qout<=i3;
end xlcs;