con_fsk.vhd

来自「通信基带信号发生器的设计」· VHDL 代码 · 共 27 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY CON_FSK IS 
PORT(CLK,QIN:IN STD_LOGIC;

     FM_OUT:OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
	);
END ENTITY;

ARCHITECTURE BEHAV OF CON_FSK IS
BEGIN


PROCESS(CLK)
BEGIN
IF CLK'EVENT AND CLK='1' THEN
   IF QIN='1' THEN
      FM_OUT<="000000000000000000000000"; 
   ELSE
      FM_OUT<="100000000000000000000000";   --0.39M的频差
   END IF;
END IF;
END PROCESS;

END;