signal.map.summary

通信基带信号发生器的设计

Analysis & Synthesis Status : Successful - Tue Oct 15 10:52:28 2002
Quartus II Version : 6.0 Build 202 06/20/2006 SP 1 SJ Full Version
Revision Name : SIGNAL
Top-level Entity Name : FINAL
Family : Cyclone
Total logic elements : 1,334
Total pins : 22
Total virtual pins : 0
Total memory bits : 36,608
Total PLLs : 1