parallel.vhd

来自「通信基带信号发生器的设计」· VHDL 代码 · 共 45 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY PARALLEL IS
PORT(MCU_IN:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
     EN,TXD:IN STD_LOGIC;
    
     SEL:OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
     FRE:OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
     FREZ:OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
     );
END ENTITY;

ARCHITECTURE BEHAV OF PARALLEL IS
SIGNAL TEMP0,TEMP1,TEMP2,TEMP3:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN

PROCESS(EN,TXD)
BEGIN
IF EN='1' THEN
   IF TXD'EVENT AND TXD='1' THEN
      TEMP0<=TEMP1; 
      TEMP1<=TEMP2;
      TEMP2<=TEMP3;
      TEMP3<=MCU_IN;
   END IF;
END IF;
END PROCESS;

PROCESS(EN,TXD)
BEGIN
IF EN'EVENT AND EN='0' THEN
  IF TEMP0="11100111" THEN
      SEL<=TEMP1(2)&TEMP1(1)&TEMP1(0);
  ELSIF TEMP0="11100110" THEN
      FRE<=TEMP3&TEMP2&TEMP1;
  ELSE
     FREZ<=TEMP3&TEMP2&TEMP1;
  END IF;
END IF;
END PROCESS;

END;