dds51.tan.rpt

DDs直接数字频率合成器的源代码

; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
+---------------------------------------------------------+-----------+----------------------------------+----------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------+------------------------------------------+--------------+
; Type                                                    ; Slack     ; Required Time                    ; Actual Time                      ; From                                                                                                                                                                                                                                                          ; To                                                                                                                                                                                                    ; From Clock                               ; To Clock                                 ; Failed Paths ;
+---------------------------------------------------------+-----------+----------------------------------+----------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------+------------------------------------------+--------------+
; Worst-case tsu                                          ; N/A       ; None                             ; 1.082 ns                         ; altera_internal_jtag                                                                                                                                                                                                                                          ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_p0u:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[3]                                   ; --                                       ; altera_internal_jtag~TCKUTAP             ; 0            ;
; Worst-case tco                                          ; N/A       ; None                             ; 8.585 ns                         ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_p0u:auto_generated|altsyncram_6r92:altsyncram1|q_a[4]                                                                                                                                                ; q_out[4]                                                                                                                                                                                              ; clk                                      ; --                                       ; 0            ;
; Worst-case tpd                                          ; N/A       ; None                             ; 2.124 ns                         ; altera_internal_jtag~TDO                                                                                                                                                                                                                                      ; altera_reserved_tdo                                                                                                                                                                                   ; --                                       ; --                                       ; 0            ;
; Worst-case th                                           ; N/A       ; None                             ; 3.659 ns                         ; altera_internal_jtag                                                                                                                                                                                                                                          ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[26] ; --                                       ; altera_internal_jtag~TCKUTAP             ; 0            ;
; Clock Setup: 'clk'                                      ; -0.969 ns ; 40.00 MHz ( period = 25.000 ns ) ; N/A                              ; lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0]                                                                                                                                               ; AddrLock:inst3|ADDRLOCK[29]                                                                                                                                                                           ; DPLL:inst4|altpll:altpll_component|_clk0 ; clk                                      ; 132          ;
; Clock Setup: 'DPLL:inst4|altpll:altpll_component|_clk0' ; 6.638 ns  ; 80.00 MHz ( period = 12.500 ns ) ; N/A                              ; AddrLock:inst3|ADDRLOCK[19]                                                                                                                                                                                                                                   ; lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[13]                                                                                      ; clk                                      ; DPLL:inst4|altpll:altpll_component|_clk0 ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP'             ; N/A       ; None                             ; 80.80 MHz ( period = 12.376 ns ) ; sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[2]                                                                                                                                                                                                            ; sld_hub:sld_hub_inst|hub_tdo                                                                                                                                                                          ; altera_internal_jtag~TCKUTAP             ; altera_internal_jtag~TCKUTAP             ; 0            ;
; Clock Hold: 'clk'                                       ; 0.873 ns  ; 40.00 MHz ( period = 25.000 ns ) ; N/A                              ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1|holdff ; sld_signaltap:auto_signaltap_0|acq_data_in_pipe_reg[2][2]                                                                                                                                             ; clk                                      ; clk                                      ; 0            ;
; Clock Hold: 'DPLL:inst4|altpll:altpll_component|_clk0'  ; 3.623 ns  ; 80.00 MHz ( period = 12.500 ns ) ; N/A                              ; AddrLock:inst3|ADDRLOCK[1]                                                                                                                                                                                                                                    ; lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[1]                                                                                         ; clk                                      ; DPLL:inst4|altpll:altpll_component|_clk0 ; 0            ;
; Total number of failed paths                            ;           ;                                  ;                                  ;                                                                                                                                                                                                                                                               ;                                                                                                                                                                                                       ;                                          ;                                          ; 132          ;
+---------------------------------------------------------+-----------+----------------------------------+----------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------+------------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C3T144C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                           ;
+------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+