prev_cmp_dds.tan.qmsg

DDs直接数字频率合成器的源代码

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[2\] register sld_hub:sld_hub_inst\|hub_tdo_reg 70.0 MHz 14.286 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 70.0 MHz between source register \"sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[2\]\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo_reg\" (period= 14.286 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.844 ns + Longest register register " "Info: + Longest register to register delay is 6.844 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[2\] 1 REG LC_X19_Y6_N8 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X19_Y6_N8; Fanout = 3; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[2\]'" {  } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] } "NODE_NAME" } } { "d:/altera/quartus72/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "d:/altera/quartus72/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.771 ns) + CELL(0.590 ns) 1.361 ns lpm_constant0:inst2\|lpm_constant0_lpm_constant_ama:lpm_constant0_lpm_constant_ama_component\|sld_mod_ram_rom:mgl_prim1\|process2~42 2 COMB LC_X19_Y6_N1 2 " "Info: 2: + IC(0.771 ns) + CELL(0.590 ns) = 1.361 ns; Loc. = LC_X19_Y6_N1; Fanout = 2; COMB Node = 'lpm_constant0:inst2\|lpm_constant0_lpm_constant_ama:lpm_constant0_lpm_constant_ama_component\|sld_mod_ram_rom:mgl_prim1\|process2~42'" {  } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "1.361 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] lpm_constant0:inst2|lpm_constant0_lpm_constant_ama:lpm_constant0_lpm_constant_ama_component|sld_mod_ram_rom:mgl_prim1|process2~42 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.245 ns) + CELL(0.114 ns) 2.720 ns sld_hub:sld_hub_inst\|hub_tdo_reg~1056 3 COMB LC_X19_Y5_N7 1 " "Info: 3: + IC(1.245 ns) + CELL(0.114 ns) = 2.720 ns; Loc. = LC_X19_Y5_N7; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg~1056'" {  } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "1.359 ns" { lpm_constant0:inst2|lpm_constant0_lpm_constant_ama:lpm_constant0_lpm_constant_ama_component|sld_mod_ram_rom:mgl_prim1|process2~42 sld_hub:sld_hub_inst|hub_tdo_reg~1056 } "NODE_NAME" } } { "d:/altera/quartus72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.230 ns) + CELL(0.590 ns) 4.540 ns sld_hub:sld_hub_inst\|hub_tdo_reg~1058 4 COMB LC_X19_Y4_N1 1 " "Info: 4: + IC(1.230 ns) + CELL(0.590 ns) = 4.540 ns; Loc. = LC_X19_Y4_N1; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg~1058'" {  } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "1.820 ns" { sld_hub:sld_hub_inst|hub_tdo_reg~1056 sld_hub:sld_hub_inst|hub_tdo_reg~1058 } "NODE_NAME" } } { "d:/altera/quartus72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.566 ns) + CELL(0.738 ns) 6.844 ns sld_hub:sld_hub_inst\|hub_tdo_reg 5 REG LC_X17_Y3_N4 1 " "Info: 5: + IC(1.566 ns) + CELL(0.738 ns) = 6.844 ns; Loc. = LC_X17_Y3_N4; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg'" {  } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "2.304 ns" { sld_hub:sld_hub_inst|hub_tdo_reg~1058 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "d:/altera/quartus72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.032 ns ( 29.69 % ) " "Info: Total cell delay = 2.032 ns ( 29.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.812 ns ( 70.31 % ) " "Info: Total interconnect delay = 4.812 ns ( 70.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "6.844 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] lpm_constant0:inst2|lpm_constant0_lpm_constant_ama:lpm_constant0_lpm_constant_ama_component|sld_mod_ram_rom:mgl_prim1|process2~42 sld_hub:sld_hub_inst|hub_tdo_reg~1056 sld_hub:sld_hub_inst|hub_tdo_reg~1058 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "6.844 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] {} lpm_constant0:inst2|lpm_constant0_lpm_constant_ama:lpm_constant0_lpm_constant_ama_component|sld_mod_ram_rom:mgl_prim1|process2~42 {} sld_hub:sld_hub_inst|hub_tdo_reg~1056 {} sld_hub:sld_hub_inst|hub_tdo_reg~1058 {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 0.771ns 1.245ns 1.230ns 1.566ns } { 0.000ns 0.590ns 0.114ns 0.590ns 0.738ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.038 ns - Smallest " "Info: - Smallest clock skew is -0.038 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.234 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.234 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y6_N1 394 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 394; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.523 ns) + CELL(0.711 ns) 5.234 ns sld_hub:sld_hub_inst\|hub_tdo_reg 2 REG LC_X17_Y3_N4 1 " "Info: 2: + IC(4.523 ns) + CELL(0.711 ns) = 5.234 ns; Loc. = LC_X17_Y3_N4; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg'" {  } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "5.234 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "d:/altera/quartus72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 13.58 % ) " "Info: Total cell delay = 0.711 ns ( 13.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.523 ns ( 86.42 % ) " "Info: Total interconnect delay = 4.523 ns ( 86.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "5.234 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "5.234 ns" { altera_internal_jtag~TCKUTAP {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 4.523ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 5.272 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 5.272 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y6_N1 394 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 394; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.561 ns) + CELL(0.711 ns) 5.272 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[2\] 2 REG LC_X19_Y6_N8 3 " "Info: 2: + IC(4.561 ns) + CELL(0.711 ns) = 5.272 ns; Loc. = LC_X19_Y6_N8; Fanout = 3; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[2\]'" {  } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] } "NODE_NAME" } } { "d:/altera/quartus72/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "d:/altera/quartus72/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 13.49 % ) " "Info: Total cell delay = 0.711 ns ( 13.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.561 ns ( 86.51 % ) " "Info: Total interconnect delay = 4.561 ns ( 86.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] } "NODE_NAME" } } { "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "5.272 ns" { altera_internal_jtag~TCKUTAP {} sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] {} } { 0.000ns 4.561ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "5.234 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "5.234 ns" { altera_internal_jtag~TCKUTAP {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 4.523ns } { 0.000ns 0.711ns } "" } } { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] } "NODE_NAME" } } { "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "5.272 ns" { altera_internal_jtag~TCKUTAP {} sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] {} } { 0.000ns 4.561ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "d:/altera/quartus72/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "d:/altera/quartus72/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "d:/altera/quartus72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "d:/altera/quartus72/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "d:/altera/quartus72/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } { "d:/altera/quartus72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "6.844 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] lpm_constant0:inst2|lpm_constant0_lpm_constant_ama:lpm_constant0_lpm_constant_ama_component|sld_mod_ram_rom:mgl_prim1|process2~42 sld_hub:sld_hub_inst|hub_tdo_reg~1056 sld_hub:sld_hub_inst|hub_tdo_reg~1058 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "6.844 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] {} lpm_constant0:inst2|lpm_constant0_lpm_constant_ama:lpm_constant0_lpm_constant_ama_component|sld_mod_ram_rom:mgl_prim1|process2~42 {} sld_hub:sld_hub_inst|hub_tdo_reg~1056 {} sld_hub:sld_hub_inst|hub_tdo_reg~1058 {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 0.771ns 1.245ns 1.230ns 1.566ns } { 0.000ns 0.590ns 0.114ns 0.590ns 0.738ns } "" } } { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "5.234 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "5.234 ns" { altera_internal_jtag~TCKUTAP {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 4.523ns } { 0.000ns 0.711ns } "" } } { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] } "NODE_NAME" } } { "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "5.272 ns" { altera_internal_jtag~TCKUTAP {} sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] {} } { 0.000ns 4.561ns } { 0.000ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "DPLL:inst4\|altpll:altpll_component\|_clk0 register AddrLock:inst3\|ADDROUT\[8\] register lpm_add_pharse:inst1\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[15\] 3.549 ns " "Info: Minimum slack time is 3.549 ns for clock \"DPLL:inst4\|altpll:altpll_component\|_clk0\" between source register \"AddrLock:inst3\|ADDROUT\[8\]\" and destination register \"lpm_add_pharse:inst1\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[15\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.043 ns + Shortest register register " "Info: + Shortest register to register delay is 1.043 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns AddrLock:inst3\|ADDROUT\[8\] 1 REG LC_X17_Y7_N7 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y7_N7; Fanout = 3; REG Node = 'AddrLock:inst3\|ADDROUT\[8\]'" {  } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "" { AddrLock:inst3|ADDROUT[8] } "NODE_NAME" } } { "AddrLock.vhd" "" { Text "E:/yezi/design/dds/AddrLock.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.734 ns) + CELL(0.309 ns) 1.043 ns lpm_add_pharse:inst1\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[15\] 2 REG LC_X18_Y7_N7 1 " "Info: 2: + IC(0.734 ns) + CELL(0.309 ns) = 1.043 ns; Loc. = LC_X18_Y7_N7; Fanout = 1; REG Node = 'lpm_add_pharse:inst1\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[15\]'" {  } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "1.043 ns" { AddrLock:inst3|ADDROUT[8] lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[15] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus72/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns ( 29.63 % ) " "Info: Total cell delay = 0.309 ns ( 29.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.734 ns ( 70.37 % ) " "Info: Total interconnect delay = 0.734 ns ( 70.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFlo