📄 prev_cmp_dds.tan.qmsg
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{ "Info" "ITDB_FULL_SLACK_RESULT" "DPLL:inst4\|altpll:altpll_component\|_clk0 register AddrLock:inst3\|ADDRLOCK\[3\] register lpm_add_pharse:inst1\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[13\] 6.755 ns " "Info: Slack time is 6.755 ns for clock \"DPLL:inst4\|altpll:altpll_component\|_clk0\" between source register \"AddrLock:inst3\|ADDRLOCK\[3\]\" and destination register \"lpm_add_pharse:inst1\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[13\]\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "9.942 ns + Largest register register " "Info: + Largest register to register requirement is 9.942 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "10.667 ns + " "Info: + Setup relationship between source and destination is 10.667 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 10.667 ns " "Info: + Latch edge is 10.667 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination DPLL:inst4\|altpll:altpll_component\|_clk0 12.500 ns -1.833 ns 50 " "Info: Clock period of Destination clock \"DPLL:inst4\|altpll:altpll_component\|_clk0\" is 12.500 ns with offset of -1.833 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk 25.000 ns 0.000 ns 50 " "Info: Clock period of Source clock \"clk\" is 25.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.464 ns + Largest " "Info: + Largest clock skew is -0.464 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "DPLL:inst4\|altpll:altpll_component\|_clk0 destination 2.318 ns + Shortest register " "Info: + Shortest clock path from clock \"DPLL:inst4\|altpll:altpll_component\|_clk0\" to destination register is 2.318 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DPLL:inst4\|altpll:altpll_component\|_clk0 1 CLK PLL_1 33 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 33; CLK Node = 'DPLL:inst4\|altpll:altpll_component\|_clk0'" { } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DPLL:inst4|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/quartus72/quartus/libraries/megafunctions/altpll.tdf" 900 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.607 ns) + CELL(0.711 ns) 2.318 ns lpm_add_pharse:inst1\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[13\] 2 REG LC_X16_Y8_N5 1 " "Info: 2: + IC(1.607 ns) + CELL(0.711 ns) = 2.318 ns; Loc. = LC_X16_Y8_N5; Fanout = 1; REG Node = 'lpm_add_pharse:inst1\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[13\]'" { } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "2.318 ns" { DPLL:inst4|altpll:altpll_component|_clk0 lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[13] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus72/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 30.67 % ) " "Info: Total cell delay = 0.711 ns ( 30.67 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.607 ns ( 69.33 % ) " "Info: Total interconnect delay = 1.607 ns ( 69.33 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "2.318 ns" { DPLL:inst4|altpll:altpll_component|_clk0 lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[13] } "NODE_NAME" } } { "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "2.318 ns" { DPLL:inst4|altpll:altpll_component|_clk0 {} lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[13] {} } { 0.000ns 1.607ns } { 0.000ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.782 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 318 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 318; CLK Node = 'clk'" { } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dds.bdf" "" { Schematic "E:/yezi/design/dds/dds.bdf" { { 80 16 184 96 "clk" "" } { 184 208 248 200 "clk" "" } { 184 504 536 200 "clk" "" } { 496 -8 32 512 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns AddrLock:inst3\|ADDRLOCK\[3\] 2 REG LC_X20_Y9_N2 3 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X20_Y9_N2; Fanout = 3; REG Node = 'AddrLock:inst3\|ADDRLOCK\[3\]'" { } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "1.313 ns" { clk AddrLock:inst3|ADDRLOCK[3] } "NODE_NAME" } } { "AddrLock.vhd" "" { Text "E:/yezi/design/dds/AddrLock.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk AddrLock:inst3|ADDRLOCK[3] } "NODE_NAME" } } { "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk {} clk~out0 {} AddrLock:inst3|ADDRLOCK[3] {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "2.318 ns" { DPLL:inst4|altpll:altpll_component|_clk0 lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[13] } "NODE_NAME" } } { "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "2.318 ns" { DPLL:inst4|altpll:altpll_component|_clk0 {} lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[13] {} } { 0.000ns 1.607ns } { 0.000ns 0.711ns } "" } } { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk AddrLock:inst3|ADDRLOCK[3] } "NODE_NAME" } } { "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk {} clk~out0 {} AddrLock:inst3|ADDRLOCK[3] {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" { } { { "AddrLock.vhd" "" { Text "E:/yezi/design/dds/AddrLock.vhd" 18 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" { } { { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus72/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "2.318 ns" { DPLL:inst4|altpll:altpll_component|_clk0 lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[13] } "NODE_NAME" } } { "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "2.318 ns" { DPLL:inst4|altpll:altpll_component|_clk0 {} lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[13] {} } { 0.000ns 1.607ns } { 0.000ns 0.711ns } "" } } { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk AddrLock:inst3|ADDRLOCK[3] } "NODE_NAME" } } { "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk {} clk~out0 {} AddrLock:inst3|ADDRLOCK[3] {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.187 ns - Longest register register " "Info: - Longest register to register delay is 3.187 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns AddrLock:inst3\|ADDRLOCK\[3\] 1 REG LC_X20_Y9_N2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y9_N2; Fanout = 3; REG Node = 'AddrLock:inst3\|ADDRLOCK\[3\]'" { } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "" { AddrLock:inst3|ADDRLOCK[3] } "NODE_NAME" } } { "AddrLock.vhd" "" { Text "E:/yezi/design/dds/AddrLock.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.139 ns) + CELL(0.575 ns) 1.714 ns lpm_add_pharse:inst1\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[3\]~112COUT1_138 2 COMB LC_X16_Y9_N5 2 " "Info: 2: + IC(1.139 ns) + CELL(0.575 ns) = 1.714 ns; Loc. = LC_X16_Y9_N5; Fanout = 2; COMB Node = 'lpm_add_pharse:inst1\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[3\]~112COUT1_138'" { } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "1.714 ns" { AddrLock:inst3|ADDRLOCK[3] lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[3]~112COUT1_138 } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus72/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.794 ns lpm_add_pharse:inst1\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[4\]~110COUT1_140 3 COMB LC_X16_Y9_N6 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.794 ns; Loc. = LC_X16_Y9_N6; Fanout = 2; COMB Node = 'lpm_add_pharse:inst1\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[4\]~110COUT1_140'" { } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[3]~112COUT1_138 lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[4]~110COUT1_140 } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus72/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.874 ns lpm_add_pharse:inst1\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[5\]~108COUT1_142 4 COMB LC_X16_Y9_N7 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.874 ns; Loc. = LC_X16_Y9_N7; Fanout = 2; COMB Node = 'lpm_add_pharse:inst1\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[5\]~108COUT1_142'" { } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[4]~110COUT1_140 lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[5]~108COUT1_142 } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus72/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.954 ns lpm_add_pharse:inst1\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[6\]~106COUT1_144 5 COMB LC_X16_Y9_N8 2 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 1.954 ns; Loc. = LC_X16_Y9_N8; Fanout = 2; COMB Node = 'lpm_add_pharse:inst1\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[6\]~106COUT1_144'" { } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[5]~108COUT1_142 lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[6]~106COUT1_144 } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus72/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 2.212 ns lpm_add_pharse:inst1\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[7\]~104 6 COMB LC_X16_Y9_N9 6 " "Info: 6: + IC(0.000 ns) + CELL(0.258 ns) = 2.212 ns; Loc. = LC_X16_Y9_N9; Fanout = 6; COMB Node = 'lpm_add_pharse:inst1\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[7\]~104'" { } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "0.258 ns" { lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[6]~106COUT1_144 lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[7]~104 } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus72/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 2.348 ns lpm_add_pharse:inst1\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[12\]~94 7 COMB LC_X16_Y8_N4 4 " "Info: 7: + IC(0.000 ns) + CELL(0.136 ns) = 2.348 ns; Loc. = LC_X16_Y8_N4; Fanout = 4; COMB Node = 'lpm_add_pharse:inst1\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[12\]~94'" { } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[7]~104 lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[12]~94 } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus72/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 3.187 ns lpm_add_pharse:inst1\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[13\] 8 REG LC_X16_Y8_N5 1 " "Info: 8: + IC(0.000 ns) + CELL(0.839 ns) = 3.187 ns; Loc. = LC_X16_Y8_N5; Fanout = 1; REG Node = 'lpm_add_pharse:inst1\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[13\]'" { } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "0.839 ns" { lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[12]~94 lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[13] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus72/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.048 ns ( 64.26 % ) " "Info: Total cell delay = 2.048 ns ( 64.26 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.139 ns ( 35.74 % ) " "Info: Total interconnect delay = 1.139 ns ( 35.74 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "3.187 ns" { AddrLock:inst3|ADDRLOCK[3] lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[3]~112COUT1_138 lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[4]~110COUT1_140 lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[5]~108COUT1_142 lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[6]~106COUT1_144 lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[7]~104 lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[12]~94 lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[13] } "NODE_NAME" } } { "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "3.187 ns" { AddrLock:inst3|ADDRLOCK[3] {} lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[3]~112COUT1_138 {} lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[4]~110COUT1_140 {} lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[5]~108COUT1_142 {} lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[6]~106COUT1_144 {} lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[7]~104 {} lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[12]~94 {} lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[13] {} } { 0.000ns 1.139ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.575ns 0.080ns 0.080ns 0.080ns 0.258ns 0.136ns 0.839ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "2.318 ns" { DPLL:inst4|altpll:altpll_component|_clk0 lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[13] } "NODE_NAME" } } { "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "2.318 ns" { DPLL:inst4|altpll:altpll_component|_clk0 {} lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[13] {} } { 0.000ns 1.607ns } { 0.000ns 0.711ns } "" } } { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk AddrLock:inst3|ADDRLOCK[3] } "NODE_NAME" } } { "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk {} clk~out0 {} AddrLock:inst3|ADDRLOCK[3] {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "3.187 ns" { AddrLock:inst3|ADDRLOCK[3] lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[3]~112COUT1_138 lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[4]~110COUT1_140 lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[5]~108COUT1_142 lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[6]~106COUT1_144 lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[7]~104 lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[12]~94 lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[13] } "NODE_NAME" } } { "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "3.187 ns" { AddrLock:inst3|ADDRLOCK[3] {} lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[3]~112COUT1_138 {} lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[4]~110COUT1_140 {} lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[5]~108COUT1_142 {} lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[6]~106COUT1_144 {} lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[7]~104 {} lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[12]~94 {} lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[13] {} } { 0.000ns 1.139ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.575ns 0.080ns 0.080ns 0.080ns 0.258ns 0.136ns 0.839ns } "" } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "clk register lpm_add_pharse:inst1\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[0\] register AddrLock:inst3\|ADDROUT\[8\] -967 ps " "Info: Slack time is -967 ps for clock \"clk\" between source register \"lpm_add_pharse:inst1\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[0\]\" and destination register \"AddrLock:inst3\|ADDROUT\[8\]\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "2.036 ns + Largest register register " "Info: + Largest register to register requirement is 2.036 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "1.833 ns + " "Info: + Setup relationship between source and destination is 1.833 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 12.500 ns " "Info: + Latch edge is 12.500 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk 25.000 ns 0.000 ns 50 " "Info: Clock period of Destination clock \"clk\" is 25.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 10.667 ns " "Info: - Launch edge is 10.667 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source DPLL:inst4\|altpll:altpll_component\|_clk0 12.500 ns -1.833 ns 50 " "Info: Clock period of Source clock \"DPLL:inst4\|altpll:altpll_component\|_clk0\" is 12.500 ns with offset of -1.833 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.464 ns + Largest " "Info: + Largest clock skew is 0.464 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.782 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 318 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 318; CLK Node = 'clk'" { } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dds.bdf" "" { Schematic "E:/yezi/design/dds/dds.bdf" { { 80 16 184 96 "clk" "" } { 184 208 248 200 "clk" "" } { 184 504 536 200 "clk" "" } { 496 -8 32 512 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns AddrLock:inst3\|ADDROUT\[8\] 2 REG LC_X17_Y7_N7 3 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X17_Y7_N7; Fanout = 3; REG Node = 'AddrLock:inst3\|ADDROUT\[8\]'" { } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "1.313 ns" { clk AddrLock:inst3|ADDROUT[8] } "NODE_NAME" } } { "AddrLock.vhd" "" { Text "E:/yezi/design/dds/AddrLock.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk AddrLock:inst3|ADDROUT[8] } "NODE_NAME" } } { "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk {} clk~out0 {} AddrLock:inst3|ADDROUT[8] {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "DPLL:inst4\|altpll:altpll_component\|_clk0 source 2.318 ns - Longest register " "Info: - Longest clock path from clock \"DPLL:inst4\|altpll:altpll_component\|_clk0\" to source register is 2.318 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DPLL:inst4\|altpll:altpll_component\|_clk0 1 CLK PLL_1 33 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 33; CLK Node = 'DPLL:inst4\|altpll:altpll_component\|_clk0'" { } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DPLL:inst4|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/quartus72/quartus/libraries/megafunctions/altpll.tdf" 900 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.607 ns) + CELL(0.711 ns) 2.318 ns lpm_add_pharse:inst1\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[0\] 2 REG LC_X18_Y8_N2 3 " "Info: 2: + IC(1.607 ns) + CELL(0.711 ns) = 2.318 ns; Loc. = LC_X18_Y8_N2; Fanout = 3; REG Node = 'lpm_add_pharse:inst1\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[0\]'" { } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "2.318 ns" { DPLL:inst4|altpll:altpll_component|_clk0 lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus72/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 30.67 % ) " "Info: Total cell delay = 0.711 ns ( 30.67 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.607 ns ( 69.33 % ) " "Info: Total interconnect delay = 1.607 ns ( 69.33 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "2.318 ns" { DPLL:inst4|altpll:altpll_component|_clk0 lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0] } "NODE_NAME" } } { "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "2.318 ns" { DPLL:inst4|altpll:altpll_component|_clk0 {} lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0] {} } { 0.000ns 1.607ns } { 0.000ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk AddrLock:inst3|ADDROUT[8] } "NODE_NAME" } } { "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk {} clk~out0 {} AddrLock:inst3|ADDROUT[8] {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "2.318 ns" { DPLL:inst4|altpll:altpll_component|_clk0 lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0] } "NODE_NAME" } } { "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "2.318 ns" { DPLL:inst4|altpll:altpll_component|_clk0 {} lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0] {} } { 0.000ns 1.607ns } { 0.000ns 0.711ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" { } { { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus72/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" { } { { "AddrLock.vhd" "" { Text "E:/yezi/design/dds/AddrLock.vhd" 18 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk AddrLock:inst3|ADDROUT[8] } "NODE_NAME" } } { "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk {} clk~out0 {} AddrLock:inst3|ADDROUT[8] {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "2.318 ns" { DPLL:inst4|altpll:altpll_component|_clk0 lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0] } "NODE_NAME" } } { "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "2.318 ns" { DPLL:inst4|altpll:altpll_component|_clk0 {} lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0] {} } { 0.000ns 1.607ns } { 0.000ns 0.711ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.003 ns - Longest register register " "Info: - Longest register to register delay is 3.003 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_add_pharse:inst1\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[0\] 1 REG LC_X18_Y8_N2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X18_Y8_N2; Fanout = 3; REG Node = 'lpm_add_pharse:inst1\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[0\]'" { } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus72/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.141 ns) + CELL(0.423 ns) 1.564 ns AddrLock:inst3\|ADDRLOCK\[16\]~80 2 COMB LC_X17_Y8_N2 2 " "Info: 2: + IC(1.141 ns) + CELL(0.423 ns) = 1.564 ns; Loc. = LC_X17_Y8_N2; Fanout = 2; COMB Node = 'AddrLock:inst3\|ADDRLOCK\[16\]~80'" { } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "1.564 ns" { lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0] AddrLock:inst3|ADDRLOCK[16]~80 } "NODE_NAME" } } { "AddrLock.vhd" "" { Text "E:/yezi/design/dds/AddrLock.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.642 ns AddrLock:inst3\|ADDRLOCK\[17\]~78 3 COMB LC_X17_Y8_N3 2 " "Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.642 ns; Loc. = LC_X17_Y8_N3; Fanout = 2; COMB Node = 'AddrLock:inst3\|ADDRLOCK\[17\]~78'" { } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "0.078 ns" { AddrLock:inst3|ADDRLOCK[16]~80 AddrLock:inst3|ADDRLOCK[17]~78 } "NODE_NAME" } } { "AddrLock.vhd" "" { Text "E:/yezi/design/dds/AddrLock.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 1.820 ns AddrLock:inst3\|ADDRLOCK\[18\]~76 4 COMB LC_X17_Y8_N4 6 " "Info: 4: + IC(0.000 ns) + CELL(0.178 ns) = 1.820 ns; Loc. = LC_X17_Y8_N4; Fanout = 6; COMB Node = 'AddrLock:inst3\|ADDRLOCK\[18\]~76'" { } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "0.178 ns" { AddrLock:inst3|ADDRLOCK[17]~78 AddrLock:inst3|ADDRLOCK[18]~76 } "NODE_NAME" } } { "AddrLock.vhd" "" { Text "E:/yezi/design/dds/AddrLock.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 2.028 ns AddrLock:inst3\|ADDROUT\[0\]~46 5 COMB LC_X17_Y8_N9 6 " "Info: 5: + IC(0.000 ns) + CELL(0.208 ns) = 2.028 ns; Loc. = LC_X17_Y8_N9; Fanout = 6; COMB Node = 'AddrLock:inst3\|ADDROUT\[0\]~46'" { } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "0.208 ns" { AddrLock:inst3|ADDRLOCK[18]~76 AddrLock:inst3|ADDROUT[0]~46 } "NODE_NAME" } } { "AddrLock.vhd" "" { Text "E:/yezi/design/dds/AddrLock.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 2.164 ns AddrLock:inst3\|ADDROUT\[5\]~56 6 COMB LC_X17_Y7_N4 3 " "Info: 6: + IC(0.000 ns) + CELL(0.136 ns) = 2.164 ns; Loc. = LC_X17_Y7_N4; Fanout = 3; COMB Node = 'AddrLock:inst3\|ADDROUT\[5\]~56'" { } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { AddrLock:inst3|ADDROUT[0]~46 AddrLock:inst3|ADDROUT[5]~56 } "NODE_NAME" } } { "AddrLock.vhd" "" { Text "E:/yezi/design/dds/AddrLock.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 3.003 ns AddrLock:inst3\|ADDROUT\[8\] 7 REG LC_X17_Y7_N7 3 " "Info: 7: + IC(0.000 ns) + CELL(0.839 ns) = 3.003 ns; Loc. = LC_X17_Y7_N7; Fanout = 3; REG Node = 'AddrLock:inst3\|ADDROUT\[8\]'" { } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "0.839 ns" { AddrLock:inst3|ADDROUT[5]~56 AddrLock:inst3|ADDROUT[8] } "NODE_NAME" } } { "AddrLock.vhd" "" { Text "E:/yezi/design/dds/AddrLock.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.862 ns ( 62.00 % ) " "Info: Total cell delay = 1.862 ns ( 62.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.141 ns ( 38.00 % ) " "Info: Total interconnect delay = 1.141 ns ( 38.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "3.003 ns" { lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0] AddrLock:inst3|ADDRLOCK[16]~80 AddrLock:inst3|ADDRLOCK[17]~78 AddrLock:inst3|ADDRLOCK[18]~76 AddrLock:inst3|ADDROUT[0]~46 AddrLock:inst3|ADDROUT[5]~56 AddrLock:inst3|ADDROUT[8] } "NODE_NAME" } } { "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "3.003 ns" { lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0] {} AddrLock:inst3|ADDRLOCK[16]~80 {} AddrLock:inst3|ADDRLOCK[17]~78 {} AddrLock:inst3|ADDRLOCK[18]~76 {} AddrLock:inst3|ADDROUT[0]~46 {} AddrLock:inst3|ADDROUT[5]~56 {} AddrLock:inst3|ADDROUT[8] {} } { 0.000ns 1.141ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.423ns 0.078ns 0.178ns 0.208ns 0.136ns 0.839ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk AddrLock:inst3|ADDROUT[8] } "NODE_NAME" } } { "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk {} clk~out0 {} AddrLock:inst3|ADDROUT[8] {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "2.318 ns" { DPLL:inst4|altpll:altpll_component|_clk0 lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0] } "NODE_NAME" } } { "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "2.318 ns" { DPLL:inst4|altpll:altpll_component|_clk0 {} lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0] {} } { 0.000ns 1.607ns } { 0.000ns 0.711ns } "" } } { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "3.003 ns" { lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0] AddrLock:inst3|ADDRLOCK[16]~80 AddrLock:inst3|ADDRLOCK[17]~78 AddrLock:inst3|ADDRLOCK[18]~76 AddrLock:inst3|ADDROUT[0]~46 AddrLock:inst3|ADDROUT[5]~56 AddrLock:inst3|ADDROUT[8] } "NODE_NAME" } } { "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus72/quartus/bin/Technology_Viewer.qrui" "3.003 ns" { lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0] {} AddrLock:inst3|ADDRLOCK[16]~80 {} AddrLock:inst3|ADDRLOCK[17]~78 {} AddrLock:inst3|ADDRLOCK[18]~76 {} AddrLock:inst3|ADDROUT[0]~46 {} AddrLock:inst3|ADDROUT[5]~56 {} AddrLock:inst3|ADDROUT[8] {} } { 0.000ns 1.141ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.423ns 0.078ns 0.178ns 0.208ns 0.136ns 0.839ns } "" } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
{ "Warning" "WTAN_FULL_REQUIREMENTS_NOT_MET" "Clock Setup: 'clk' 129 " "Warning: Can't achieve timing requirement Clock Setup: 'clk' along 129 path(s). See Report window for details." { } { } 0 0 "Can't achieve timing requirement %1!s! along %2!d! path(s). See Report window for details." 0 0 "" 0}
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