addrlock.vhd

来自「DDs直接数字频率合成器的源代码」· VHDL 代码 · 共 24 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;		
USE IEEE.STD_LOGIC_UNSIGNED.ALL;	

ENTITY AddrLock IS
	PORT (ADDRIN   : IN STD_LOGIC_VECTOR(32 - 1 DOWNTO 0);	-- 输入地址
		  CLK      : IN STD_LOGIC;							-- 系统时钟
		  ADDROUT  : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);		-- 地址输出（相位位数）
		  ADDRLOCK : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0));	-- 锁存地址（累加器输出）
END AddrLock;

ARCHITECTURE RTL OF AddrLock IS

BEGIN
	
	PROCESS (ADDRIN, CLK)
	BEGIN
		IF CLK'EVENT AND CLK = '1' THEN
			ADDRLOCK <= ADDRIN;
			ADDROUT <= ADDRIN(32 - 1 DOWNTO 32 - 9);
		END IF;
	END PROCESS;

END RTL;