dds.map.eqn

DDs直接数字频率合成器的源代码

RB1_constant_update_reg[22] = AMPP_FUNCTION(A1L5, RB1_constant_shift_reg[22], VCC, RB1L73);


--PB8_sout_node[5] is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[5]
--operation mode is arithmetic

PB8_sout_node[5]_carry_eqn = PB8L11;
PB8_sout_node[5]_lut_out = RB1_constant_update_reg[21] $ F1_ADDRLOCK[21] $ PB8_sout_node[5]_carry_eqn;
PB8_sout_node[5] = DFFEAS(PB8_sout_node[5]_lut_out, SB1__clk0, VCC, , , , , , );

--PB8L13 is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[5]~153
--operation mode is arithmetic

PB8L13 = CARRY(RB1_constant_update_reg[21] & !F1_ADDRLOCK[21] & !PB8L11 # !RB1_constant_update_reg[21] & (!PB8L11 # !F1_ADDRLOCK[21]));


--F1_ADDRLOCK[20] is AddrLock:inst3|ADDRLOCK[20]
--operation mode is arithmetic

F1_ADDRLOCK[20]_carry_eqn = F1L25;
F1_ADDRLOCK[20]_lut_out = PB8_sout_node[4] $ (!F1_ADDRLOCK[20]_carry_eqn);
F1_ADDRLOCK[20] = DFFEAS(F1_ADDRLOCK[20]_lut_out, clk, VCC, , , , , , );

--F1L27 is AddrLock:inst3|ADDRLOCK[20]~179
--operation mode is arithmetic

F1L27 = CARRY(PB8_sout_node[4] & (!F1L25));


--RB1_constant_shift_reg[24] is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|constant_shift_reg[24]
--operation mode is normal

RB1_constant_shift_reg[24] = AMPP_FUNCTION(A1L5, RB1_constant_shift_reg[25], RB1_constant_update_reg[24], VB1_state[4], RB1L76, VCC, RB1L19);


--RB1_constant_shift_reg[25] is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|constant_shift_reg[25]
--operation mode is normal

RB1_constant_shift_reg[25] = AMPP_FUNCTION(A1L5, RB1_constant_shift_reg[26], RB1_constant_update_reg[25], VB1_state[4], RB1L76, VCC, RB1L19);


--RB1_constant_shift_reg[26] is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|constant_shift_reg[26]
--operation mode is normal

RB1_constant_shift_reg[26] = AMPP_FUNCTION(A1L5, RB1_constant_shift_reg[27], RB1_constant_update_reg[26], VB1_state[4], RB1L76, VCC, RB1L19);


--RB1_constant_shift_reg[27] is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|constant_shift_reg[27]
--operation mode is normal

RB1_constant_shift_reg[27] = AMPP_FUNCTION(A1L5, RB1_constant_shift_reg[28], RB1_constant_update_reg[27], VB1_state[4], RB1L76, VCC, RB1L19);


--RB1_constant_shift_reg[28] is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|constant_shift_reg[28]
--operation mode is normal

RB1_constant_shift_reg[28] = AMPP_FUNCTION(A1L5, RB1_constant_shift_reg[29], RB1_constant_update_reg[28], VB1_state[4], RB1L76, VCC, RB1L19);


--RB1_constant_shift_reg[29] is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|constant_shift_reg[29]
--operation mode is normal

RB1_constant_shift_reg[29] = AMPP_FUNCTION(A1L5, RB1_constant_shift_reg[30], RB1_constant_update_reg[29], VB1_state[4], RB1L76, VCC, RB1L19);


--RB1_constant_shift_reg[30] is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|constant_shift_reg[30]
--operation mode is normal

RB1_constant_shift_reg[30] = AMPP_FUNCTION(A1L5, RB1_constant_shift_reg[31], RB1_constant_update_reg[30], VB1_state[4], RB1L76, VCC, RB1L19);


--RB1_constant_shift_reg[31] is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|constant_shift_reg[31]
--operation mode is normal

RB1_constant_shift_reg[31] = AMPP_FUNCTION(A1L5, altera_internal_jtag, RB1_constant_update_reg[31], VB1_state[4], RB1L76, VCC, RB1L19);


--VB1_state[6] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[6]
--operation mode is normal

VB1_state[6] = AMPP_FUNCTION(A1L5, VB1_state[5], VB1_state[6], VCC, A1L7);


--VB1_state[1] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[1]
--operation mode is normal

VB1_state[1] = AMPP_FUNCTION(A1L5, VB1_state[0], VB1_state[8], VB1_state[1], VB1_state[15], VCC, A1L7);


--VB1_state[15] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[15]
--operation mode is normal

VB1_state[15] = AMPP_FUNCTION(A1L5, VB1_state[12], VB1_state[14], VCC, !A1L7);


--VB1_state[11] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[11]
--operation mode is normal

VB1_state[11] = AMPP_FUNCTION(A1L5, VB1_state[11], VB1_state[10], VB1_state[14], VCC, A1L7);


--VB1_state[9] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[9]
--operation mode is normal

VB1_state[9] = AMPP_FUNCTION(A1L5, A1L7, VB1_state[2], VCC);


--VB1_tms_cnt[2] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[2]
--operation mode is normal

VB1_tms_cnt[2] = AMPP_FUNCTION(A1L5, VB1_tms_cnt[2], VB1_tms_cnt[1], VB1_tms_cnt[0], VCC, !A1L7);


--VB1_tms_cnt[1] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[1]
--operation mode is normal

VB1_tms_cnt[1] = AMPP_FUNCTION(A1L5, VB1_tms_cnt[1], VB1_tms_cnt[0], VCC, !A1L7);


--VB1_tms_cnt[0] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[0]
--operation mode is normal

VB1_tms_cnt[0] = AMPP_FUNCTION(A1L5, A1L7, VB1_tms_cnt[0], VCC);


--VB1L19 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~243
--operation mode is normal

VB1L19 = AMPP_FUNCTION(VB1_tms_cnt[2], VB1_tms_cnt[1], VB1_tms_cnt[0]);


--VB1_state[10] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[10]
--operation mode is normal

VB1_state[10] = AMPP_FUNCTION(A1L5, VB1_state[9], A1L7, VCC);


--TB1_Q[0] is sld_hub:sld_hub_inst|sld_dffex:RESET|Q[0]
--operation mode is normal

TB1_Q[0] = AMPP_FUNCTION(A1L5, TB1_Q[0], WB1_dffe1a[7], TB1L3, TB2_Q[0], H1_jtag_debug_mode_usr1);


--L1L18 is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|sld_rom_sr:\constant_logic_gen:name_gen:info_rom_sr|WORD_SR~552
--operation mode is normal

L1L18 = AMPP_FUNCTION(L1L17, L1_word_counter[0], L1_word_counter[3]);


--L1L19 is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|sld_rom_sr:\constant_logic_gen:name_gen:info_rom_sr|WORD_SR~553
--operation mode is normal

L1L19 = AMPP_FUNCTION(L1L18, L1_word_counter[1], L1_word_counter[0], L1_word_counter[2]);


--L1_WORD_SR[2] is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|sld_rom_sr:\constant_logic_gen:name_gen:info_rom_sr|WORD_SR[2]
--operation mode is normal

L1_WORD_SR[2] = AMPP_FUNCTION(A1L5, L1L20, VB1_state[4], L1_WORD_SR[3], L3_clear_signal, VCC, L1L14);


--L1L4 is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|sld_rom_sr:\constant_logic_gen:name_gen:info_rom_sr|word_counter[0]~290
--operation mode is normal

L1L4 = AMPP_FUNCTION(L1_word_counter[0], L1_word_counter[2]);


--L1L5 is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|sld_rom_sr:\constant_logic_gen:name_gen:info_rom_sr|word_counter[0]~291
--operation mode is normal

L1L5 = AMPP_FUNCTION(L1_word_counter[1], L1L4, L1_word_counter[3], L3_clear_signal);


--L1L1 is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|sld_rom_sr:\constant_logic_gen:name_gen:info_rom_sr|add~121
--operation mode is normal

L1L1 = AMPP_FUNCTION(L1_word_counter[0], L1_word_counter[1]);


--L1L6 is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|sld_rom_sr:\constant_logic_gen:name_gen:info_rom_sr|word_counter[0]~293
--operation mode is normal

L1L6 = AMPP_FUNCTION(RB1L72, H1L30, VB1_state[4], L3_clear_signal);


--H1L29 is sld_hub:sld_hub_inst|jtag_debug_mode~171
--operation mode is normal

H1L29 = AMPP_FUNCTION(VB1_state[12], A1L7, VB1_state[2]);


--WB1_dffe1a[1] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_9ie:auto_generated|dffe1a[1]
--operation mode is normal

WB1_dffe1a[1] = AMPP_FUNCTION(A1L5, TB3_Q[1], H1L28, TB3_Q[2], TB3_Q[3], H1_CLRN_SIGNAL, H1L3);


--TB2L3 is sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0]~52
--operation mode is normal

TB2L3 = AMPP_FUNCTION(TB9_Q[0], WB1_dffe1a[1]);


--TB1L3 is sld_hub:sld_hub_inst|sld_dffex:RESET|Q[0]~59
--operation mode is normal

TB1L3 = AMPP_FUNCTION(VB1_state[8], H1_OK_TO_UPDATE_IR_Q);


--H1L5 is sld_hub:sld_hub_inst|GEN_SHADOW_IRF~1
--operation mode is normal

H1L5 = AMPP_FUNCTION(TB8_Q[0], H1_OK_TO_UPDATE_IR_Q, VB1_state[5]);


--Z1_status_out[1] is sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out[1]
--operation mode is normal

Z1_status_out[1] = AMPP_FUNCTION(clk, Z1L5, !B1_reset_all);


--Y1_buffer_write_enable is sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_state_machine:sm1|buffer_write_enable
--operation mode is normal

Y1_buffer_write_enable = AMPP_FUNCTION(clk, Y1L5, !B1_reset_all);


--M1L4 is sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|ela_status~132
--operation mode is normal

M1L4 = AMPP_FUNCTION(Z1_status_out[1], Y1_buffer_write_enable, Q1_dffs[5]);


--RB1_ir_loaded_address_reg[0] is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|ir_loaded_address_reg[0]
--operation mode is normal

RB1_ir_loaded_address_reg[0] = AMPP_FUNCTION(A1L5, RB1_ir_loaded_address_reg[0], RB1L75, VB1_state[3], RB1L76, !RB1L74);


--Z1_status_out[2] is sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out[2]
--operation mode is normal

Z1_status_out[2] = AMPP_FUNCTION(clk, TB4_Q[1], !B1_reset_all);


--Y1_edq is sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_state_machine:sm1|edq
--operation mode is normal

Y1_edq = AMPP_FUNCTION(clk, TB4_Q[1], V1L1, Q1_dffs[4], Y1L3, !B1_reset_all);


--TB4_Q[1] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[1]
--operation mode is normal

TB4_Q[1] = AMPP_FUNCTION(A1L5, TB6_Q[1], TB3_Q[1], TB2_Q[0], H1_CLRN_SIGNAL, H1L23);


--M1L5 is sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|ela_status~133
--operation mode is normal

M1L5 = AMPP_FUNCTION(Y1_post_trigger_count_enable, Y1_edq, N1_is_max_write_address_ff, TB4_Q[1]);


--M1L6 is sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|ela_status~134
--operation mode is normal

M1L6 = AMPP_FUNCTION(Z1_status_out[2], M1L5, Q1_dffs[5]);


--RB1_constant_shift_reg[2] is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|constant_shift_reg[2]
--operation mode is normal

RB1_constant_shift_reg[2] = AMPP_FUNCTION(A1L5, RB1_constant_shift_reg[3], RB1_constant_update_reg[2], VB1_state[4], RB1L76, VCC, RB1L19);


--RB1_constant_update_reg[1] is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|constant_update_reg[1]
--operation mode is normal

RB1_constant_update_reg[1] = AMPP_FUNCTION(A1L5, RB1_constant_shift_reg[1], VCC, RB1L73);


--HB1_cout is sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_0id:auto_generated|cout
--operation mode is normal

HB1_cout = AMPP_FUNCTION(HB1L20);


--Z1L5 is sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out~113
--operation mode is normal

Z1L5 = AMPP_FUNCTION(TB4_Q[1], HB1_cout, N1_is_max_write_address_ff);


--X1_trigger_happened_ff[0] is sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened_ff[0]
--operation mode is normal

X1_trigger_happened_ff[0] = AMPP_FUNCTION(clk, N1_is_max_write_address_ff, Q1_dffs[5], X1_trigger_happened_ff[0], TB4_Q[1]);


--BB1_regoutff is sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:9:sm1|regoutff
--operation mode is normal

BB1_regoutff = AMPP_FUNCTION(clk, B1_acq_trigger_in_reg[9], BB1L2, Q2_dffs[29], BB1_holdff, VCC);


--BB10_regoutff is sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|regoutff
--operation mode is normal

BB10_regoutff = AMPP_FUNCTION(clk, B1_acq_trigger_in_reg[0], BB10L2, Q2_dffs[2], BB10_holdff, VCC);


--BB9_regoutff is sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1|regoutff
--operation mode is normal

BB9_regoutff = AMPP_FUNCTION(clk, B1_acq_trigger_in_reg[1], BB9L2, Q2_dffs[5], BB9_holdff, VCC);


--X1L4 is sld_signaltap:auto_signaltap_0|sld_ela_control:ela_contr