dds.map.eqn

DDs直接数字频率合成器的源代码

PB8L15 = CARRY(RB1_constant_update_reg[22] & (F1_ADDRLOCK[22] # !PB8L13) # !RB1_constant_update_reg[22] & F1_ADDRLOCK[22] & !PB8L13);


--F1_ADDRLOCK[21] is AddrLock:inst3|ADDRLOCK[21]
--operation mode is arithmetic

F1_ADDRLOCK[21]_carry_eqn = F1L27;
F1_ADDRLOCK[21]_lut_out = PB8_sout_node[5] $ (F1_ADDRLOCK[21]_carry_eqn);
F1_ADDRLOCK[21] = DFFEAS(F1_ADDRLOCK[21]_lut_out, clk, VCC, , , , , , );

--F1L29 is AddrLock:inst3|ADDRLOCK[21]~175
--operation mode is arithmetic

F1L29 = CARRY(!F1L27 # !PB8_sout_node[5]);


--RB1_constant_update_reg[24] is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|constant_update_reg[24]
--operation mode is normal

RB1_constant_update_reg[24] = AMPP_FUNCTION(A1L5, RB1_constant_shift_reg[24], VCC, RB1L73);


--RB1_constant_update_reg[25] is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|constant_update_reg[25]
--operation mode is normal

RB1_constant_update_reg[25] = AMPP_FUNCTION(A1L5, RB1_constant_shift_reg[25], VCC, RB1L73);


--RB1_constant_update_reg[26] is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|constant_update_reg[26]
--operation mode is normal

RB1_constant_update_reg[26] = AMPP_FUNCTION(A1L5, RB1_constant_shift_reg[26], VCC, RB1L73);


--RB1_constant_update_reg[27] is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|constant_update_reg[27]
--operation mode is normal

RB1_constant_update_reg[27] = AMPP_FUNCTION(A1L5, RB1_constant_shift_reg[27], VCC, RB1L73);


--RB1_constant_update_reg[28] is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|constant_update_reg[28]
--operation mode is normal

RB1_constant_update_reg[28] = AMPP_FUNCTION(A1L5, RB1_constant_shift_reg[28], VCC, RB1L73);


--RB1_constant_update_reg[29] is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|constant_update_reg[29]
--operation mode is normal

RB1_constant_update_reg[29] = AMPP_FUNCTION(A1L5, RB1_constant_shift_reg[29], VCC, RB1L73);


--RB1_constant_update_reg[30] is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|constant_update_reg[30]
--operation mode is normal

RB1_constant_update_reg[30] = AMPP_FUNCTION(A1L5, RB1_constant_shift_reg[30], VCC, RB1L73);


--RB1_constant_update_reg[31] is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|constant_update_reg[31]
--operation mode is normal

RB1_constant_update_reg[31] = AMPP_FUNCTION(A1L5, RB1_constant_shift_reg[31], VCC, RB1L73);


--VB1_state[7] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[7]
--operation mode is normal

VB1_state[7] = AMPP_FUNCTION(A1L5, A1L7, VB1_state[6], VCC);


--VB1_state[2] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[2]
--operation mode is normal

VB1_state[2] = AMPP_FUNCTION(A1L5, VB1_state[8], VB1_state[1], VB1_state[15], VCC, !A1L7);


--Q5_dffs[1] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[1]
--operation mode is normal

Q5_dffs[1] = AMPP_FUNCTION(A1L5, Q5_dffs[2], VB1_state[0], VB1_state[11]);


--Q5_dffs[9] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[9]
--operation mode is normal

Q5_dffs[9] = AMPP_FUNCTION(A1L5, altera_internal_jtag, VB1_state[0], VB1_state[11]);


--Q5_dffs[8] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[8]
--operation mode is normal

Q5_dffs[8] = AMPP_FUNCTION(A1L5, Q5_dffs[9], VB1_state[0], VB1_state[11]);


--Q5_dffs[7] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[7]
--operation mode is normal

Q5_dffs[7] = AMPP_FUNCTION(A1L5, Q5_dffs[8], VB1_state[0], VB1_state[11]);


--Q5_dffs[6] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[6]
--operation mode is normal

Q5_dffs[6] = AMPP_FUNCTION(A1L5, Q5_dffs[7], VB1_state[0], VB1_state[11]);


--A1L30 is rtl~93
--operation mode is normal

A1L30 = !Q5_dffs[9] & !Q5_dffs[8] & !Q5_dffs[7] & !Q5_dffs[6];


--Q5_dffs[3] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[3]
--operation mode is normal

Q5_dffs[3] = AMPP_FUNCTION(A1L5, Q5_dffs[4], VB1_state[0], VB1_state[11]);


--Q5_dffs[2] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[2]
--operation mode is normal

Q5_dffs[2] = AMPP_FUNCTION(A1L5, Q5_dffs[3], VB1_state[0], VB1_state[11]);


--Q5_dffs[5] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[5]
--operation mode is normal

Q5_dffs[5] = AMPP_FUNCTION(A1L5, Q5_dffs[6], VB1_state[0], VB1_state[11]);


--Q5_dffs[4] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[4]
--operation mode is normal

Q5_dffs[4] = AMPP_FUNCTION(A1L5, Q5_dffs[5], VB1_state[0], VB1_state[11]);


--A1L31 is rtl~94
--operation mode is normal

A1L31 = Q5_dffs[3] & Q5_dffs[2] & !Q5_dffs[5] & !Q5_dffs[4];


--Q5_dffs[0] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[0]
--operation mode is normal

Q5_dffs[0] = AMPP_FUNCTION(A1L5, Q5_dffs[1], VB1_state[0], VB1_state[11]);


--VB1_state[0] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0]
--operation mode is normal

VB1_state[0] = AMPP_FUNCTION(A1L5, A1L7, VB1_state[9], VB1L19, VB1_state[0], VCC);


--VB1_state[12] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[12]
--operation mode is normal

VB1_state[12] = AMPP_FUNCTION(A1L5, VB1_state[11], VB1_state[10], VCC, !A1L7);


--TB3_Q[8] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[8]
--operation mode is normal

TB3_Q[8] = AMPP_FUNCTION(A1L5, altera_internal_jtag, H1_CLRN_SIGNAL, VB1_state[4], H1L24);


--H1_CLRN_SIGNAL is sld_hub:sld_hub_inst|CLRN_SIGNAL
--operation mode is normal

H1_CLRN_SIGNAL = AMPP_FUNCTION(A1L5, VB1_state[1], TB1_Q[0], VCC);


--H1_OK_TO_UPDATE_IR_Q is sld_hub:sld_hub_inst|OK_TO_UPDATE_IR_Q
--operation mode is normal

H1_OK_TO_UPDATE_IR_Q = AMPP_FUNCTION(A1L5, H1_jtag_debug_mode_usr1, H1_OK_TO_UPDATE_IR_Q, VB1_state[4], VB1_state[8], VCC);


--H1L20 is sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21
--operation mode is normal

H1L20 = AMPP_FUNCTION(A1L7, VB1_state[4], H1_jtag_debug_mode_usr1, H1_OK_TO_UPDATE_IR_Q);


--L1_WORD_SR[1] is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|sld_rom_sr:\constant_logic_gen:name_gen:info_rom_sr|WORD_SR[1]
--operation mode is normal

L1_WORD_SR[1] = AMPP_FUNCTION(A1L5, L1L19, VB1_state[4], L1_WORD_SR[2], L3_clear_signal, VCC, L1L14);


--L1_word_counter[3] is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|sld_rom_sr:\constant_logic_gen:name_gen:info_rom_sr|word_counter[3]
--operation mode is normal

L1_word_counter[3] = AMPP_FUNCTION(A1L5, L1L5, L1_word_counter[3], L1_word_counter[2], L1L1, VCC, L1L6);


--L1_word_counter[1] is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|sld_rom_sr:\constant_logic_gen:name_gen:info_rom_sr|word_counter[1]
--operation mode is normal

L1_word_counter[1] = AMPP_FUNCTION(A1L5, L1L5, L1_word_counter[0], L1_word_counter[1], VCC, L1L6);


--L1_word_counter[2] is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|sld_rom_sr:\constant_logic_gen:name_gen:info_rom_sr|word_counter[2]
--operation mode is normal

L1_word_counter[2] = AMPP_FUNCTION(A1L5, L1_word_counter[0], L1_word_counter[1], L1L5, L1_word_counter[2], VCC, L1L6);


--L1_word_counter[0] is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|sld_rom_sr:\constant_logic_gen:name_gen:info_rom_sr|word_counter[0]
--operation mode is normal

L1_word_counter[0] = AMPP_FUNCTION(A1L5, L1_word_counter[0], L1L5, VCC, L1L6);


--L1L16 is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|sld_rom_sr:\constant_logic_gen:name_gen:info_rom_sr|WORD_SR~549
--operation mode is normal

L1L16 = AMPP_FUNCTION(L1_word_counter[3], L1_word_counter[1], L1_word_counter[2], L1_word_counter[0]);


--L3_clear_signal is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|clear_signal
--operation mode is normal

L3_clear_signal = AMPP_FUNCTION(VB1_state[8], H1_jtag_debug_mode_usr1);


--H1_jtag_debug_mode is sld_hub:sld_hub_inst|jtag_debug_mode
--operation mode is normal

H1_jtag_debug_mode = AMPP_FUNCTION(A1L5, H1L28, H1_jtag_debug_mode, H1L29, VB1_state[15], VB1_state[0]);


--TB2_Q[0] is sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0]
--operation mode is normal

TB2_Q[0] = AMPP_FUNCTION(A1L5, TB2L3, TB2_Q[0], TB1L3, H1L22, H1_CLRN_SIGNAL);


--H1L30 is sld_hub:sld_hub_inst|node_ena~39
--operation mode is normal

H1L30 = AMPP_FUNCTION(TB8_Q[0], H1_jtag_debug_mode, TB2_Q[0]);


--TB7_Q[1] is sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF|Q[1]
--operation mode is normal

TB7_Q[1] = AMPP_FUNCTION(A1L5, TB3_Q[1], H1_CLRN_SIGNAL, H1L5);


--TB3_Q[1] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[1]
--operation mode is normal

TB3_Q[1] = AMPP_FUNCTION(A1L5, M1L4, RB1_ir_loaded_address_reg[0], TB3_Q[2], H1L19, H1_CLRN_SIGNAL, VB1_state[4], TB3L4);


--VB1_state[5] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[5]
--operation mode is normal

VB1_state[5] = AMPP_FUNCTION(A1L5, A1L7, VB1_state[4], VB1_state[3], VCC);


--H1L6 is sld_hub:sld_hub_inst|GEN_SHADOW_IRF~18
--operation mode is normal

H1L6 = AMPP_FUNCTION(H1_OK_TO_UPDATE_IR_Q, VB1_state[5]);


--WB1_dffe1a[2] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_9ie:auto_generated|dffe1a[2]
--operation mode is normal

WB1_dffe1a[2] = AMPP_FUNCTION(A1L5, TB3_Q[2], H1L28, TB3_Q[1], TB3_Q[3], H1_CLRN_SIGNAL, H1L3);


--H1L22 is sld_hub:sld_hub_inst|IRF_ENABLE[2]~111
--operation mode is normal

H1L22 = AMPP_FUNCTION(TB9_Q[0], WB1_dffe1a[2]);


--H1L21 is sld_hub:sld_hub_inst|IRF_ENABLE[1]~112
--operation mode is normal

H1L21 = AMPP_FUNCTION(H1L6, H1L22, TB8_Q[0], TB2_Q[0]);


--TB7_Q[2] is sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF|Q[2]
--operation mode is normal

TB7_Q[2] = AMPP_FUNCTION(A1L5, TB3_Q[2], H1_CLRN_SIGNAL, H1L5);


--TB3_Q[2] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[2]
--operation mode is normal

TB3_Q[2] = AMPP_FUNCTION(A1L5, M1L6, TB3_Q[3], H1L19, H1_CLRN_SIGNAL, VB1_state[4], TB3L4);


--TB7_Q[0] is sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF|Q[0]
--operation mode is normal

TB7_Q[0] = AMPP_FUNCTION(A1L5, TB3_Q[0], H1_CLRN_SIGNAL, H1L5);


--RB1_constant_shift_reg[1] is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|constant_shift_reg[1]
--operation mode is normal

RB1_constant_shift_reg[1] = AMPP_FUNCTION(A1L5, RB1_constant_shift_reg[2], RB1_constant_update_reg[1], VB1_state[4], RB1L76, VCC, RB1L19);


--RB1_constant_update_reg[0] is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|constant_update_reg[0]
--operation mode is normal

RB1_constant_update_reg[0] = AMPP_FUNCTION(A1L5, RB1_constant_shift_reg[0], VCC, RB1L73);


--RB1L76 is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|sdr~12
--operation mode is normal