dds.map.eqn

DDs直接数字频率合成器的源代码

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--JB1_q_a[9] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_pas:auto_generated|q_a[9]
--RAM Block Operation Mode: ROM
--Port A Depth: 512, Port A Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
JB1_q_a[9]_PORT_A_address = BUS(F1_ADDRLOCK[23], F1_ADDRLOCK[24], F1_ADDRLOCK[25], F1_ADDRLOCK[26], F1_ADDRLOCK[27], F1_ADDRLOCK[28], F1_ADDRLOCK[29], F1_ADDRLOCK[30], F1_ADDROUT[8]);
JB1_q_a[9]_PORT_A_address_reg = DFFE(JB1_q_a[9]_PORT_A_address, JB1_q_a[9]_clock_0, , , );
JB1_q_a[9]_clock_0 = clk;
JB1_q_a[9]_PORT_A_data_out = MEMORY(, , JB1_q_a[9]_PORT_A_address_reg, , , , , , JB1_q_a[9]_clock_0, , , , , );
JB1_q_a[9]_PORT_A_data_out_reg = DFFE(JB1_q_a[9]_PORT_A_data_out, JB1_q_a[9]_clock_0, , , );
JB1_q_a[9] = JB1_q_a[9]_PORT_A_data_out_reg[0];


--JB1_q_a[8] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_pas:auto_generated|q_a[8]
--RAM Block Operation Mode: ROM
--Port A Depth: 512, Port A Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
JB1_q_a[8]_PORT_A_address = BUS(F1_ADDRLOCK[23], F1_ADDRLOCK[24], F1_ADDRLOCK[25], F1_ADDRLOCK[26], F1_ADDRLOCK[27], F1_ADDRLOCK[28], F1_ADDRLOCK[29], F1_ADDRLOCK[30], F1_ADDROUT[8]);
JB1_q_a[8]_PORT_A_address_reg = DFFE(JB1_q_a[8]_PORT_A_address, JB1_q_a[8]_clock_0, , , );
JB1_q_a[8]_clock_0 = clk;
JB1_q_a[8]_PORT_A_data_out = MEMORY(, , JB1_q_a[8]_PORT_A_address_reg, , , , , , JB1_q_a[8]_clock_0, , , , , );
JB1_q_a[8]_PORT_A_data_out_reg = DFFE(JB1_q_a[8]_PORT_A_data_out, JB1_q_a[8]_clock_0, , , );
JB1_q_a[8] = JB1_q_a[8]_PORT_A_data_out_reg[0];


--JB1_q_a[7] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_pas:auto_generated|q_a[7]
--RAM Block Operation Mode: ROM
--Port A Depth: 512, Port A Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
JB1_q_a[7]_PORT_A_address = BUS(F1_ADDRLOCK[23], F1_ADDRLOCK[24], F1_ADDRLOCK[25], F1_ADDRLOCK[26], F1_ADDRLOCK[27], F1_ADDRLOCK[28], F1_ADDRLOCK[29], F1_ADDRLOCK[30], F1_ADDROUT[8]);
JB1_q_a[7]_PORT_A_address_reg = DFFE(JB1_q_a[7]_PORT_A_address, JB1_q_a[7]_clock_0, , , );
JB1_q_a[7]_clock_0 = clk;
JB1_q_a[7]_PORT_A_data_out = MEMORY(, , JB1_q_a[7]_PORT_A_address_reg, , , , , , JB1_q_a[7]_clock_0, , , , , );
JB1_q_a[7]_PORT_A_data_out_reg = DFFE(JB1_q_a[7]_PORT_A_data_out, JB1_q_a[7]_clock_0, , , );
JB1_q_a[7] = JB1_q_a[7]_PORT_A_data_out_reg[0];


--JB1_q_a[6] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_pas:auto_generated|q_a[6]
--RAM Block Operation Mode: ROM
--Port A Depth: 512, Port A Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
JB1_q_a[6]_PORT_A_address = BUS(F1_ADDRLOCK[23], F1_ADDRLOCK[24], F1_ADDRLOCK[25], F1_ADDRLOCK[26], F1_ADDRLOCK[27], F1_ADDRLOCK[28], F1_ADDRLOCK[29], F1_ADDRLOCK[30], F1_ADDROUT[8]);
JB1_q_a[6]_PORT_A_address_reg = DFFE(JB1_q_a[6]_PORT_A_address, JB1_q_a[6]_clock_0, , , );
JB1_q_a[6]_clock_0 = clk;
JB1_q_a[6]_PORT_A_data_out = MEMORY(, , JB1_q_a[6]_PORT_A_address_reg, , , , , , JB1_q_a[6]_clock_0, , , , , );
JB1_q_a[6]_PORT_A_data_out_reg = DFFE(JB1_q_a[6]_PORT_A_data_out, JB1_q_a[6]_clock_0, , , );
JB1_q_a[6] = JB1_q_a[6]_PORT_A_data_out_reg[0];


--JB1_q_a[5] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_pas:auto_generated|q_a[5]
--RAM Block Operation Mode: ROM
--Port A Depth: 512, Port A Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
JB1_q_a[5]_PORT_A_address = BUS(F1_ADDRLOCK[23], F1_ADDRLOCK[24], F1_ADDRLOCK[25], F1_ADDRLOCK[26], F1_ADDRLOCK[27], F1_ADDRLOCK[28], F1_ADDRLOCK[29], F1_ADDRLOCK[30], F1_ADDROUT[8]);
JB1_q_a[5]_PORT_A_address_reg = DFFE(JB1_q_a[5]_PORT_A_address, JB1_q_a[5]_clock_0, , , );
JB1_q_a[5]_clock_0 = clk;
JB1_q_a[5]_PORT_A_data_out = MEMORY(, , JB1_q_a[5]_PORT_A_address_reg, , , , , , JB1_q_a[5]_clock_0, , , , , );
JB1_q_a[5]_PORT_A_data_out_reg = DFFE(JB1_q_a[5]_PORT_A_data_out, JB1_q_a[5]_clock_0, , , );
JB1_q_a[5] = JB1_q_a[5]_PORT_A_data_out_reg[0];


--JB1_q_a[4] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_pas:auto_generated|q_a[4]
--RAM Block Operation Mode: ROM
--Port A Depth: 512, Port A Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
JB1_q_a[4]_PORT_A_address = BUS(F1_ADDRLOCK[23], F1_ADDRLOCK[24], F1_ADDRLOCK[25], F1_ADDRLOCK[26], F1_ADDRLOCK[27], F1_ADDRLOCK[28], F1_ADDRLOCK[29], F1_ADDRLOCK[30], F1_ADDROUT[8]);
JB1_q_a[4]_PORT_A_address_reg = DFFE(JB1_q_a[4]_PORT_A_address, JB1_q_a[4]_clock_0, , , );
JB1_q_a[4]_clock_0 = clk;
JB1_q_a[4]_PORT_A_data_out = MEMORY(, , JB1_q_a[4]_PORT_A_address_reg, , , , , , JB1_q_a[4]_clock_0, , , , , );
JB1_q_a[4]_PORT_A_data_out_reg = DFFE(JB1_q_a[4]_PORT_A_data_out, JB1_q_a[4]_clock_0, , , );
JB1_q_a[4] = JB1_q_a[4]_PORT_A_data_out_reg[0];


--JB1_q_a[3] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_pas:auto_generated|q_a[3]
--RAM Block Operation Mode: ROM
--Port A Depth: 512, Port A Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
JB1_q_a[3]_PORT_A_address = BUS(F1_ADDRLOCK[23], F1_ADDRLOCK[24], F1_ADDRLOCK[25], F1_ADDRLOCK[26], F1_ADDRLOCK[27], F1_ADDRLOCK[28], F1_ADDRLOCK[29], F1_ADDRLOCK[30], F1_ADDROUT[8]);
JB1_q_a[3]_PORT_A_address_reg = DFFE(JB1_q_a[3]_PORT_A_address, JB1_q_a[3]_clock_0, , , );
JB1_q_a[3]_clock_0 = clk;
JB1_q_a[3]_PORT_A_data_out = MEMORY(, , JB1_q_a[3]_PORT_A_address_reg, , , , , , JB1_q_a[3]_clock_0, , , , , );
JB1_q_a[3]_PORT_A_data_out_reg = DFFE(JB1_q_a[3]_PORT_A_data_out, JB1_q_a[3]_clock_0, , , );
JB1_q_a[3] = JB1_q_a[3]_PORT_A_data_out_reg[0];


--JB1_q_a[2] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_pas:auto_generated|q_a[2]
--RAM Block Operation Mode: ROM
--Port A Depth: 512, Port A Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
JB1_q_a[2]_PORT_A_address = BUS(F1_ADDRLOCK[23], F1_ADDRLOCK[24], F1_ADDRLOCK[25], F1_ADDRLOCK[26], F1_ADDRLOCK[27], F1_ADDRLOCK[28], F1_ADDRLOCK[29], F1_ADDRLOCK[30], F1_ADDROUT[8]);
JB1_q_a[2]_PORT_A_address_reg = DFFE(JB1_q_a[2]_PORT_A_address, JB1_q_a[2]_clock_0, , , );
JB1_q_a[2]_clock_0 = clk;
JB1_q_a[2]_PORT_A_data_out = MEMORY(, , JB1_q_a[2]_PORT_A_address_reg, , , , , , JB1_q_a[2]_clock_0, , , , , );
JB1_q_a[2]_PORT_A_data_out_reg = DFFE(JB1_q_a[2]_PORT_A_data_out, JB1_q_a[2]_clock_0, , , );
JB1_q_a[2] = JB1_q_a[2]_PORT_A_data_out_reg[0];


--JB1_q_a[1] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_pas:auto_generated|q_a[1]
--RAM Block Operation Mode: ROM
--Port A Depth: 512, Port A Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
JB1_q_a[1]_PORT_A_address = BUS(F1_ADDRLOCK[23], F1_ADDRLOCK[24], F1_ADDRLOCK[25], F1_ADDRLOCK[26], F1_ADDRLOCK[27], F1_ADDRLOCK[28], F1_ADDRLOCK[29], F1_ADDRLOCK[30], F1_ADDROUT[8]);
JB1_q_a[1]_PORT_A_address_reg = DFFE(JB1_q_a[1]_PORT_A_address, JB1_q_a[1]_clock_0, , , );
JB1_q_a[1]_clock_0 = clk;
JB1_q_a[1]_PORT_A_data_out = MEMORY(, , JB1_q_a[1]_PORT_A_address_reg, , , , , , JB1_q_a[1]_clock_0, , , , , );
JB1_q_a[1]_PORT_A_data_out_reg = DFFE(JB1_q_a[1]_PORT_A_data_out, JB1_q_a[1]_clock_0, , , );
JB1_q_a[1] = JB1_q_a[1]_PORT_A_data_out_reg[0];


--JB1_q_a[0] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_pas:auto_generated|q_a[0]
--RAM Block Operation Mode: ROM
--Port A Depth: 512, Port A Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
JB1_q_a[0]_PORT_A_address = BUS(F1_ADDRLOCK[23], F1_ADDRLOCK[24], F1_ADDRLOCK[25], F1_ADDRLOCK[26], F1_ADDRLOCK[27], F1_ADDRLOCK[28], F1_ADDRLOCK[29], F1_ADDRLOCK[30], F1_ADDROUT[8]);
JB1_q_a[0]_PORT_A_address_reg = DFFE(JB1_q_a[0]_PORT_A_address, JB1_q_a[0]_clock_0, , , );
JB1_q_a[0]_clock_0 = clk;
JB1_q_a[0]_PORT_A_data_out = MEMORY(, , JB1_q_a[0]_PORT_A_address_reg, , , , , , JB1_q_a[0]_clock_0, , , , , );
JB1_q_a[0]_PORT_A_data_out_reg = DFFE(JB1_q_a[0]_PORT_A_data_out, JB1_q_a[0]_clock_0, , , );
JB1_q_a[0] = JB1_q_a[0]_PORT_A_data_out_reg[0];


--A1L6 is altera_internal_jtag~TDO
A1L6 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !H1_hub_tdo);

--A1L7 is altera_internal_jtag~TMSUTAP
A1L7 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !H1_hub_tdo);

--A1L5 is altera_internal_jtag~TCKUTAP
A1L5 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !H1_hub_tdo);

--altera_internal_jtag is altera_internal_jtag
altera_internal_jtag = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !H1_hub_tdo);


--F1_ADDRLOCK[23] is AddrLock:inst3|ADDRLOCK[23]
--operation mode is arithmetic

F1_ADDRLOCK[23]_carry_eqn = F1L31;
F1_ADDRLOCK[23]_lut_out = PB8_sout_node[7] $ (F1_ADDRLOCK[23]_carry_eqn);
F1_ADDRLOCK[23] = DFFEAS(F1_ADDRLOCK[23]_lut_out, clk, VCC, , , , , , );

--F1L33 is AddrLock:inst3|ADDRLOCK[23]~139
--operation mode is arithmetic

F1L33 = CARRY(!F1L31 # !PB8_sout_node[7]);


--F1_ADDRLOCK[24] is AddrLock:inst3|ADDRLOCK[24]
--operation mode is arithmetic

F1_ADDRLOCK[24]_carry_eqn = F1L33;
F1_ADDRLOCK[24]_lut_out = PB8_sout_node[8] $ (!F1_ADDRLOCK[24]_carry_eqn);
F1_ADDRLOCK[24] = DFFEAS(F1_ADDRLOCK[24]_lut_out, clk, VCC, , , , , , );

--F1L35 is AddrLock:inst3|ADDRLOCK[24]~143
--operation mode is arithmetic

F1L35 = CARRY(PB8_sout_node[8] & (!F1L33));


--F1_ADDRLOCK[25] is AddrLock:inst3|ADDRLOCK[25]
--operation mode is arithmetic

F1_ADDRLOCK[25]_carry_eqn = F1L35;
F1_ADDRLOCK[25]_lut_out = PB8_sout_node[9] $ (F1_ADDRLOCK[25]_carry_eqn);
F1_ADDRLOCK[25] = DFFEAS(F1_ADDRLOCK[25]_lut_out, clk, VCC, , , , , , );

--F1L37 is AddrLock:inst3|ADDRLOCK[25]~147
--operation mode is arithmetic

F1L37 = CARRY(!F1L35 # !PB8_sout_node[9]);


--F1_ADDRLOCK[26] is AddrLock:inst3|ADDRLOCK[26]
--operation mode is arithmetic

F1_ADDRLOCK[26]_carry_eqn = F1L37;
F1_ADDRLOCK[26]_lut_out = PB8_sout_node[10] $ (!F1_ADDRLOCK[26]_carry_eqn);
F1_ADDRLOCK[26] = DFFEAS(F1_ADDRLOCK[26]_lut_out, clk, VCC, , , , , , );

--F1L39 is AddrLock:inst3|ADDRLOCK[26]~151
--operation mode is arithmetic

F1L39 = CARRY(PB8_sout_node[10] & (!F1L37));


--F1_ADDRLOCK[27] is AddrLock:inst3|ADDRLOCK[27]
--operation mode is arithmetic

F1_ADDRLOCK[27]_carry_eqn = F1L39;
F1_ADDRLOCK[27]_lut_out = PB8_sout_node[11] $ (F1_ADDRLOCK[27]_carry_eqn);
F1_ADDRLOCK[27] = DFFEAS(F1_ADDRLOCK[27]_lut_out, clk, VCC, , , , , , );

--F1L41 is AddrLock:inst3|ADDRLOCK[27]~155
--operation mode is arithmetic

F1L41 = CARRY(!F1L39 # !PB8_sout_node[11]);


--F1_ADDRLOCK[28] is AddrLock:inst3|ADDRLOCK[28]
--operation mode is arithmetic

F1_ADDRLOCK[28]_carry_eqn = F1L41;
F1_ADDRLOCK[28]_lut_out = PB8_sout_node[12] $ (!F1_ADDRLOCK[28]_carry_eqn);
F1_ADDRLOCK[28] = DFFEAS(F1_ADDRLOCK[28]_lut_out, clk, VCC, , , , , , );

--F1L43 is AddrLock:inst3|ADDRLOCK[28]~159
--operation mode is arithmetic

F1L43 = CARRY(PB8_sout_node[12] & (!F1L41));


--F1_ADDRLOCK[29] is AddrLock:inst3|ADDRLOCK[29]
--operation mode is arithmetic

F1_ADDRLOCK[29]_carry_eqn = F1L43;
F1_ADDRLOCK[29]_lut_out = PB8_sout_node[13] $ (F1_ADDRLOCK[29]_carry_eqn);
F1_ADDRLOCK[29] = DFFEAS(F1_ADDRLOCK[29]_lut_out, clk, VCC, , , , , , );

--F1L45 is AddrLock:inst3|ADDRLOCK[29]~163
--operation mode is arithmetic

F1L45 = CARRY(!F1L43 # !PB8_sout_node[13]);


--F1_ADDRLOCK[30] is AddrLock:inst3|ADDRLOCK[30]
--operation mode is arithmetic

F1_ADDRLOCK[30]_carry_eqn = F1L45;
F1_ADDRLOCK[30]_lut_out = PB8_sout_node[14] $ (!F1_ADDRLOCK[30]_carry_eqn);
F1_ADDRLOCK[30] = DFFEAS(F1_ADDRLOCK[30]_lut_out, clk, VCC, , , , , , );

--F1L47 is AddrLock:inst3|ADDRLOCK[30]~167
--operation mode is arithmetic

F1L47 = CARRY(PB8_sout_node[14] & (!F1L45));


--F1_ADDROUT[8] is AddrLock:inst3|ADDROUT[8]
--operation mode is normal

F1_ADDROUT[8]_carry_eqn = F1L47;
F1_ADDROUT[8]_lut_out = PB8_sout_node[15] $ (F1_ADDROUT[8]_carry_eqn);
F1_ADDROUT[8] = DFFEAS(F1_ADDROUT[8]_lut_out, clk, VCC, , , , , , );


--H1_hub_tdo is sld_hub:sld_hub_inst|hub_tdo
--operation mode is normal

H1_hub_tdo = AMPP_FUNCTION(!A1L5, H1L11, H1L14, H1L17, H1L18, !VB1_state[8]);


--PB8_sout_node[7] is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[7]
--operation mode is arithmetic

PB8_sout_node[7]_carry_eqn = PB8L15;
PB8_sout_node[7]_lut_out = RB1_constant_update_reg[23] $ F1_ADDRLOCK[23] $ !PB8_sout_node[7]_carry_eqn;
PB8_sout_node[7] = DFFEAS(PB8_sout_node[7]_lut_out, SB1__clk0, VCC, , , , , , );

--PB8L17 is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[7]~113
--operation mode is arithmetic

PB8L17 = CARRY(RB1_constant_update_reg[23] & (!PB8L15 # !F1_ADDRLOCK[23]) # !RB1_constant_update_reg[23] & !F1_ADDRLOCK[23] & !PB8L15);


--F1_ADDRLOCK[22] is AddrLock:inst3|ADDRLOCK[22]
--operation mode is arithmetic

F1_ADDRLOCK[22]_carry_eqn = F1L29;
F1_ADDRLOCK[22]_lut_out = PB8_sout_node[6] $ (!F1_ADDRLOCK[22]_carry_eqn);
F1_ADDRLOCK[22] = DFFEAS(F1_ADDRLOCK[22]_lut_out, clk, VCC, , , , , , );

--F1L31 is AddrLock:inst3|ADDRLOCK[22]~171
--operation mode is arithmetic

F1L31 = CARRY(PB8_sout_node[6] & (!F1L29));


--PB8_sout_node[8] is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[8]
--operation mode is arithmetic

PB8_sout_node[8]_carry_eqn = PB8L17;
PB8_sout_node[8]_lut_out = RB1_constant_update_reg[24] $ F1_ADDRLOCK[24] $ !PB8_sout_node[8]_carry_eqn;
PB8_sout_node[8] = DFFEAS(PB8_sout_node[8]_lut_out, SB1__clk0, VCC, , , , , , );

--PB8L19 is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[8]~117
--operation mode is arithmetic

PB8L19 = CARRY(RB1_constant_update_reg[24] & (F1_ADDRLOCK[24] # !PB8L17) # !RB1_constant_update_reg[24] & F1_ADDRLOCK[24] & !PB8L17);


--PB8_sout_node[9] is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[9]
--operation mode is arithmetic

PB8_sout_node[9]_carry_eqn = PB8L19;
PB8_sout_node[9]_lut_out = RB1_constant_update_reg[25] $ F1_ADDRLOCK[25] $ PB8_sout_node[9]_carry_eqn;
PB8_sout_node[9] = DFFEAS(PB8_sout_node[9]_lut_out, SB1__clk0, VCC, , , , , , );