dds.fit.rpt

DDs直接数字频率合成器的源代码

; Optimize Hold Timing                                               ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                                        ; Off                            ; Off                            ;
; Equivalent RAM and MLAB Paused Read Capabilities                   ; Care                           ; Care                           ;
; Optimize Timing                                                    ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing                         ; On                             ; On                             ;
; Limit to One Fitting Attempt                                       ; Off                            ; Off                            ;
; Final Placement Optimizations                                      ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                        ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                      ; 1                              ; 1                              ;
; Slow Slew Rate                                                     ; Off                            ; Off                            ;
; PCI I/O                                                            ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                              ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                          ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                                 ; Off                            ; Off                            ;
; Auto Packed Registers -- Cyclone                                   ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                  ; On                             ; On                             ;
; Auto Merge PLLs                                                    ; On                             ; On                             ;
; Perform Physical Synthesis for Combinational Logic for Performance ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                       ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                          ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                             ; Off                            ; Off                            ;
; Physical Synthesis Effort Level                                    ; Normal                         ; Normal                         ;
; Logic Cell Insertion - Logic Duplication                           ; Auto                           ; Auto                           ;
; Auto Register Duplication                                          ; Auto                           ; Auto                           ;
; Auto Global Clock                                                  ; On                             ; On                             ;
; Auto Global Register Control Signals                               ; On                             ; On                             ;
; Stop After Congestion Map Generation                               ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                  ; Off                            ; Off                            ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in E:/yezi/design/dds/dds.pin.


+-----------------------------------------------------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                                                                         ;
+---------------------------------------------+-------------------------------------------------------------------------+
; Resource                                    ; Usage                                                                   ;
+---------------------------------------------+-------------------------------------------------------------------------+
; Total logic elements                        ; 730 / 2,910 ( 25 % )                                                    ;
;     -- Combinational with no register       ; 146                                                                     ;
;     -- Register only                        ; 227                                                                     ;
;     -- Combinational with a register        ; 357                                                                     ;
;                                             ;                                                                         ;
; Logic element usage by number of LUT inputs ;                                                                         ;
;     -- 4 input functions                    ; 223                                                                     ;
;     -- 3 input functions                    ; 115                                                                     ;
;     -- 2 input functions                    ; 130                                                                     ;
;     -- 1 input functions                    ; 116                                                                     ;
;     -- 0 input functions                    ; 146                                                                     ;
;                                             ;                                                                         ;
; Logic elements by mode                      ;                                                                         ;
;     -- normal mode                          ; 633                                                                     ;
;     -- arithmetic mode                      ; 97                                                                      ;
;     -- qfbk mode                            ; 17                                                                      ;
;     -- register cascade mode                ; 0                                                                       ;
;     -- synchronous clear/load mode          ; 189                                                                     ;
;     -- asynchronous clear/load mode         ; 249                                                                     ;
;                                             ;                                                                         ;
; Total registers                             ; 584 / 3,210 ( 18 % )                                                    ;
; Total LABs                                  ; 90 / 291 ( 31 % )                                                       ;
; Logic elements in carry chains              ; 108                                                                     ;
; User inserted logic elements                ; 0                                                                       ;
; Virtual pins                                ; 0                                                                       ;
; I/O pins                                    ; 19 / 104 ( 18 % )                                                       ;
;     -- Clock pins                           ; 1 / 2 ( 50 % )                                                          ;
; Global signals                              ; 8                                                                       ;
; M4Ks                                        ; 5 / 13 ( 38 % )                                                         ;
; Total memory bits                           ; 15,360 / 59,904 ( 26 % )                                                ;
; Total RAM block bits                        ; 23,040 / 59,904 ( 38 % )                                                ;
; PLLs                                        ; 1 / 1 ( 100 % )                                                         ;
; Global clocks                               ; 8 / 8 ( 100 % )                                                         ;
; Average interconnect usage                  ; 4%                                                                      ;
; Peak interconnect usage                     ; 6%                                                                      ;
; Maximum fan-out node                        ; altera_internal_jtag~TDO                                                ;
; Maximum fan-out                             ; 345                                                                     ;
; Highest non-global fan-out signal           ; sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] ;
; Highest non-global fan-out                  ; 91                                                                      ;
; Total fan-out                               ; 3098                                                                    ;
; Average fan-out                             ; 4.09                                                                    ;
+---------------------------------------------+-------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                 ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; clk  ; 16    ; 1        ; 0            ; 8            ; 2           ; 219                   ; 0                  ; yes    ; no             ; no            ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; User                 ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+