dds.tan.rpt

DDs直接数字频率合成器的源代码

; Type                                                    ; Slack     ; Required Time                    ; Actual Time                      ; From                                                                                                                            ; To                                                                                                                                           ; From Clock                               ; To Clock                                 ; Failed Paths ;
+---------------------------------------------------------+-----------+----------------------------------+----------------------------------+---------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------+------------------------------------------+--------------+
; Worst-case tsu                                          ; N/A       ; None                             ; 0.433 ns                         ; altera_internal_jtag                                                                                                            ; sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_ogi:auto_generated|dffe1a[7]                                                      ; --                                       ; altera_internal_jtag~TCKUTAP             ; 0            ;
; Worst-case tco                                          ; N/A       ; None                             ; 8.600 ns                         ; lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_9d31:auto_generated|q_a[7]                                             ; q_out[7]                                                                                                                                     ; clk                                      ; --                                       ; 0            ;
; Worst-case tpd                                          ; N/A       ; None                             ; 2.124 ns                         ; altera_internal_jtag~TDO                                                                                                        ; altera_reserved_tdo                                                                                                                          ; --                                       ; --                                       ; 0            ;
; Worst-case th                                           ; N/A       ; None                             ; 3.117 ns                         ; altera_internal_jtag                                                                                                            ; lpm_constant0:inst2|lpm_constant0_lpm_constant_ama:lpm_constant0_lpm_constant_ama_component|sld_mod_ram_rom:mgl_prim1|constant_shift_reg[31] ; --                                       ; altera_internal_jtag~TCKUTAP             ; 0            ;
; Clock Setup: 'clk'                                      ; -0.960 ns ; 40.00 MHz ( period = 25.000 ns ) ; N/A                              ; lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0]                 ; AddrLock:inst3|ADDROUT[8]                                                                                                                    ; DPLL:inst4|altpll:altpll_component|_clk0 ; clk                                      ; 130          ;
; Clock Setup: 'DPLL:inst4|altpll:altpll_component|_clk0' ; 6.704 ns  ; 80.00 MHz ( period = 12.500 ns ) ; N/A                              ; AddrLock:inst3|ADDRLOCK[16]                                                                                                     ; lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[15]                             ; clk                                      ; DPLL:inst4|altpll:altpll_component|_clk0 ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP'             ; N/A       ; None                             ; 59.22 MHz ( period = 16.886 ns ) ; sld_hub:sld_hub_inst|jtag_debug_mode_usr1                                                                                       ; sld_hub:sld_hub_inst|hub_tdo_reg                                                                                                             ; altera_internal_jtag~TCKUTAP             ; altera_internal_jtag~TCKUTAP             ; 0            ;
; Clock Hold: 'clk'                                       ; 0.822 ns  ; 40.00 MHz ( period = 25.000 ns ) ; N/A                              ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|base_address[0] ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|base_address[0]              ; clk                                      ; clk                                      ; 0            ;
; Clock Hold: 'DPLL:inst4|altpll:altpll_component|_clk0'  ; 3.613 ns  ; 80.00 MHz ( period = 12.500 ns ) ; N/A                              ; AddrLock:inst3|ADDRLOCK[5]                                                                                                      ; lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[5]                                ; clk                                      ; DPLL:inst4|altpll:altpll_component|_clk0 ; 0            ;
; Total number of failed paths                            ;           ;                                  ;                                  ;                                                                                                                                 ;                                                                                                                                              ;                                          ;                                          ; 130          ;
+---------------------------------------------------------+-----------+----------------------------------+----------------------------------+---------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------+------------------------------------------+--------------+


+---------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                      ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                         ; Setting            ; From ; To ; Entity Name ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                    ; EP1C3T144C8        ;      ;    ;             ;
; Timing Models                                                  ; Final              ;      ;    ;             ;
; Default hold multicycle                                        ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                      ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                         ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                 ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                               ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                          ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                        ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                               ; Off                ;      ;    ;             ;
; Enable Clock Latency                                           ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node          ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                          ; 10                 ;      ;    ;             ;
; Number of paths to report                                      ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                   ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                         ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                     ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                   ; Off                ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis ; Off                ;      ;    ;             ;
+----------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                           ;
+------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                          ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;