dds.sim.rpt

DDs直接数字频率合成器的源代码

; Detect setup and hold time violations                           ; Off     ; Off           ;
; Detect glitches                                                 ; Off     ; Off           ;
; Automatically save/load simulation netlist                      ; Off     ; Off           ;
; Disable timing delays in Timing Simulation                      ; Off     ; Off           ;
; Generate Signal Activity File                                   ; Off     ; Off           ;
; Group bus channels in simulation results                        ; Off     ; Off           ;
; Preserve fewer signal transitions to reduce memory requirements ; On      ; On            ;
; Overwrite Waveform Inputs With Simulation Outputs               ; On      ;               ;
+-----------------------------------------------------------------+---------+---------------+


+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.


+---------------------------------------------------------------------------------------------+
; |dds|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_d4s:auto_generated|ALTSYNCRAM ;
+---------------------------------------------------------------------------------------------+
Memory report data cannot be output to ASCII.
Please use Quartus II to view the memory report data.


+--------------------------------------------------------------------+
; Coverage Summary                                                   ;
+-----------------------------------------------------+--------------+
; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;      25.84 % ;
; Total nodes checked                                 ; 115          ;
; Total output ports checked                          ; 209          ;
; Total output ports with complete 1/0-value coverage ; 54           ;
; Total output ports with no 1/0-value coverage       ; 155          ;
; Total output ports with no 1-value coverage         ; 155          ;
; Total output ports with no 0-value coverage         ; 155          ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                                                                                                                                                   ;
+-----------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                                             ; Output Port Name                                                                                                                   ; Output Port Type ;
+-----------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------+------------------+
; |dds|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_d4s:auto_generated|q_a[13]                              ; |dds|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_d4s:auto_generated|q_a[13]                                           ; portadataout0    ;
; |dds|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_d4s:auto_generated|q_a[13]                              ; |dds|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_d4s:auto_generated|q_a[11]                                           ; portadataout1    ;
; |dds|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_d4s:auto_generated|q_a[13]                              ; |dds|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_d4s:auto_generated|q_a[10]                                           ; portadataout2    ;
; |dds|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_d4s:auto_generated|q_a[13]                              ; |dds|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_d4s:auto_generated|q_a[9]                                            ; portadataout3    ;
; |dds|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_d4s:auto_generated|q_a[13]                              ; |dds|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_d4s:auto_generated|q_a[0]                                            ; portadataout4    ;
; |dds|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_d4s:auto_generated|q_a[12]                              ; |dds|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_d4s:auto_generated|q_a[12]                                           ; portadataout0    ;
; |dds|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_d4s:auto_generated|q_a[12]                              ; |dds|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_d4s:auto_generated|q_a[8]                                            ; portadataout1    ;
; |dds|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_d4s:auto_generated|q_a[12]                              ; |dds|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_d4s:auto_generated|q_a[7]                                            ; portadataout2    ;
; |dds|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_d4s:auto_generated|q_a[12]                              ; |dds|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_d4s:auto_generated|q_a[6]                                            ; portadataout3    ;
; |dds|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_d4s:auto_generated|q_a[12]                              ; |dds|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_d4s:auto_generated|q_a[5]                                            ; portadataout4    ;
; |dds|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_d4s:auto_generated|q_a[12]                              ; |dds|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_d4s:auto_generated|q_a[4]                                            ; portadataout5    ;
; |dds|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_d4s:auto_generated|q_a[12]                              ; |dds|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_d4s:auto_generated|q_a[3]                                            ; portadataout6    ;
; |dds|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_d4s:auto_generated|q_a[12]                              ; |dds|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_d4s:auto_generated|q_a[2]                                            ; portadataout7    ;
; |dds|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_d4s:auto_generated|q_a[12]                              ; |dds|lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_d4s:auto_generated|q_a[1]                                            ; portadataout8    ;
; |dds|AddrLock:inst3|ADDRLOCK[25]                                                                                      ; |dds|AddrLock:inst3|ADDRLOCK[25]                                                                                                   ; regout           ;
; |dds|AddrLock:inst3|ADDRLOCK[26]                                                                                      ; |dds|AddrLock:inst3|ADDRLOCK[26]                                                                                                   ; regout           ;
; |dds|AddrLock:inst3|ADDRLOCK[27]                                                                                      ; |dds|AddrLock:inst3|ADDRLOCK[27]                                                                                                   ; regout           ;
; |dds|AddrLock:inst3|ADDRLOCK[28]                                                                                      ; |dds|AddrLock:inst3|ADDRLOCK[28]                                                                                                   ; regout           ;
; |dds|AddrLock:inst3|ADDRLOCK[29]                                                                                      ; |dds|AddrLock:inst3|ADDRLOCK[29]                                                                                                   ; regout           ;
; |dds|AddrLock:inst3|ADDRLOCK[29]                                                                                      ; |dds|AddrLock:inst3|ADDRLOCK[29]~163COUT1_225                                                                                      ; cout1            ;