📄 第6节 verilog常用程序示例 -与非网专题： fpga开发实用教程.htm
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<DD style="FLOAT: left">更新于2008-05-28 04:40:25 </DD></DL></DIV>
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<P><STRONG>2.6.1 Verilog基本模块</STRONG> <BR><BR>1．触发器的Verilog实现
<BR><BR>时序电路是高速电路的主要应用类型，其特点是任意时刻电路产生的稳定输出不仅与当前的输入有关，而且还与电路过去时刻的输入有关。时序电路的基本单元就是触发器。下面介绍几种常见同步触发器的Verilog实现。
</P>
<UL>
<LI>同步RS触发器 </LI></UL>
<P>RS触发器分为同步触发器和异步触发器，二者的区别在于同步触发器有一个时钟端clk，只有在时钟端的信号上升（正触发）或下降（负触发）时，触发器的输出才会发生变化。下面以正触发为例，给出其Verilog代码实现。
<BR><BR>例2-15 正触发型同步RS触发器的Verilog实现。<BR><BR>module sy_rs_ff (clk, r, s, q, qb);
<BR> input clk, r, s;
<BR> output q, qb;
<BR> reg q;
<BR><BR> assign qb = ~ q;
<BR> always @(posedge clk) begin
<BR>
case({r, s})
<BR>
2'b00: q <= 0;
<BR>
2'b01: q <=
1; <BR> 2'b10:
q <= 0;
<BR>
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