rxd.v

一个基于硬件描述语言的uart核 该软核灵巧方便

////////////////////////////////////////////////////////
// File : rxd.v
// Author :xinggang xu
// Organization:
// Created : 17/4/2008      
// Last update : 21/4/2008     
// Platform :      
// Simulators :      
// Synthesizers:      
// Targets :      
// Dependency :      
/////////////////////////////////////////////////////////      
// Description:uart      
/////////////////////////////////////////////////////////      
// Copyright (C) 2008 xu      
///////////////////////////////////////////////////////////   
`timescale 1 ps / 1 ps
module rxd(//input
            bclk,
            rstr,
            rxd,
            //output
            r_readay,
            rbuf
            );
input bclk;
input rstr;
input rxd;
output r_readay;
output[7:0] rbuf;
reg r_readay;
wire rxd_sync;
reg [3:0]rcnt;
//reg [7:0]rbufs;
reg [7:0]rbufs;
reg [3:0]r_bitcnt;
reg [2:0]state;
//reg [2:0]next_state;
parameter tp=1;
parameter framelen=8;
//**************************
//reciever state   gray code
parameter r_start=3'b001;
parameter r_center=3'b010;
parameter r_wait=3'b011;
parameter r_sample=3'b100;
parameter r_stop=3'b101;
assign rxd_sync=rxd;
always @(posedge bclk or negedge rstr)
begin
    if(~rstr)  
     begin
         state<=#tp r_start;
    end
    else 
    case (state)
        r_start:if(~rxd_sync) state<=#tp r_center;
        r_center:if((~rxd_sync) && (rcnt==8))  state<=#tp r_wait;
                  else if(rxd_sync) state<=#tp r_start;
        r_wait:if(rcnt==14)
                  if(r_bitcnt==framelen) state<=#tp r_stop;
                  else state<=#tp r_sample;
        r_sample:state<=#tp r_wait;
        r_stop:state<=#tp r_start;
        default:state<=#tp r_start;
    endcase
end
always @(posedge bclk or negedge rstr)
begin
    if(~rstr)
    begin
        //rbufs<=#tp 0;
		  rbufs<=#tp 0;
      r_readay<=#tp 0;
      rcnt<=#tp 0;
      r_bitcnt<=#tp 0;
    end
    else
    case(state)
        r_start: 
          begin
            r_readay<=#tp 0;
            if(!rxd_sync) 
                 begin    
                     r_bitcnt<=#tp 0;
                     rcnt<=#tp 0;
                 end
            end    
        r_center:if(!rxd_sync)
                 begin
                     if(rcnt==8)  rcnt<=#tp 0;
                     else  rcnt<=#tp rcnt+1;  
                 end   
        r_wait:if(rcnt==14)     rcnt<=#tp 0;
               else    rcnt<=#tp rcnt+1;
        r_sample:begin
                    rbufs<=#tp {rxd_sync,rbufs[7:1]};
                    r_bitcnt<=#tp r_bitcnt+1;
                end
        r_stop: begin
                   r_readay<=#tp 1;  
                   //rbuf<=rbufs;  
                end
        default: ;
    endcase
end
assign rbuf=rbufs;
endmodule