txd.v

一个基于硬件描述语言的uart核 该软核灵巧方便

////////////////////////////////////////////////////////
// File : txd.v
// Author :xinggang xu
// Organization:
// Created : 07/05/2008      
// Last update :      
// Platform :      
// Simulators :      
// Synthesizers:      
// Targets :      
// Dependency :      
/////////////////////////////////////////////////////////      
// Description:uart      
/////////////////////////////////////////////////////////      
// Copyright (C) 2008 xu      
///////////////////////////////////////////////////////////   
`timescale 1 ps / 1 ps
module txd(//input
            bclk,
            rstr,
            t_mit,
            tbuf,
            //output
            t_done,
            txd
            );
input bclk;
input rstr;
input t_mit;
input [7:0]tbuf;
output t_done;

output txd;
reg [7:0]tbufs;
reg [3:0]tcnt;
reg txds;
reg [3:0]t_bitcnt;
reg [2:0]state;
parameter tp=1;
parameter framelen=8;
//**************************
//reciever state   
parameter t_idle=3'b001;
parameter t_start=3'b010;
parameter t_wait=3'b011;
parameter t_shift=3'b100;  
parameter t_stop=3'b101;  

assign t_done=(((state==t_stop) && tcnt==14) && ~t_mit);   
always @(posedge bclk or negedge rstr)
begin
    if(~rstr)   state<=#tp t_idle;
    else
    begin
    case(state)
        t_idle:if(t_mit) state<=#tp t_start;
               else  state<=#tp t_idle;  
        t_start:state<=#tp t_wait;  
               // else  state<=#tp t_start;   
        t_wait:if(tcnt>=14)
                  if(t_bitcnt==framelen) state<=#tp t_stop;
                  else state<=#tp t_shift;
                else state<=#tp t_wait;  
        t_shift:state<=#tp t_wait;
        t_stop:if(tcnt>=14)   
               begin
                   if(!t_mit) state<=#tp t_idle;
                   else state<=#tp t_stop;
               end
               else  state<=#tp t_stop;
        default:state<=#tp t_idle;
    endcase
    end
end
always @(posedge bclk or negedge rstr)
begin
    if(~rstr)
    begin
	    tbufs<=#tp 0;
        tcnt<=#tp 0;
        txds<=#tp 1;
        t_bitcnt<=#tp 0;
    end
    else
    case(state)  
        t_idle:
          begin
              tcnt<=#tp 0;
              t_bitcnt<=#tp 0; 
              if(t_mit) 
                begin
                  tbufs<=#tp tbuf;
                end
              else tbufs<=#tp 0;
          end
        t_start:    
          begin
            txds<=#tp 0;
            
          end    
        t_wait:if(tcnt==14)
               begin
                   tcnt<=#tp 0;
                   if(t_bitcnt==framelen) t_bitcnt<=#tp 0;
               end
               else tcnt<=#tp tcnt+1; 
        t_shift:
               begin
                   txds<=#tp tbufs[0];
                   tbufs<=#tp {1'b0,tbufs[7:1]} ;
                   t_bitcnt<=#tp t_bitcnt+1;
               end 
        t_stop: 
               begin
                    tcnt<=#tp tcnt+1;
                    txds<=#tp 1'b1;
                end
        endcase
end
assign txd=txds;
endmodule