dff_reg.tan.qmsg

来自「郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程」· QMSG 代码 · 共 10 行 · 第 1/2 页

{ "Info" "ITDB_TSU_RESULT" "Qi D CLK 3.965 ns register " "Info: tsu for register \"Qi\" (data pin = \"D\", clock pin = \"CLK\") is 3.965 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.169 ns + Longest pin register " "Info: + Longest pin to register delay is 8.169 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns D 1 PIN PIN_A6 1 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_A6; Fanout = 1; PIN Node = 'D'" {  } { { "F:/DFF_REG/db/DFF_REG_cmp.qrpt" "" { Report "F:/DFF_REG/db/DFF_REG_cmp.qrpt" Compiler "DFF_REG" "UNKNOWN" "V1" "F:/DFF_REG/db/DFF_REG.quartus_db" { Floorplan "F:/DFF_REG/" "" "" { D } "NODE_NAME" } "" } } { "DFF_REG.vhd" "" { Text "F:/DFF_REG/DFF_REG.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.385 ns) + CELL(0.309 ns) 8.169 ns Qi 2 REG LC_X1_Y16_N2 2 " "Info: 2: + IC(6.385 ns) + CELL(0.309 ns) = 8.169 ns; Loc. = LC_X1_Y16_N2; Fanout = 2; REG Node = 'Qi'" {  } { { "F:/DFF_REG/db/DFF_REG_cmp.qrpt" "" { Report "F:/DFF_REG/db/DFF_REG_cmp.qrpt" Compiler "DFF_REG" "UNKNOWN" "V1" "F:/DFF_REG/db/DFF_REG.quartus_db" { Floorplan "F:/DFF_REG/" "" "6.694 ns" { D Qi } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.784 ns 21.84 % " "Info: Total cell delay = 1.784 ns ( 21.84 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.385 ns 78.16 % " "Info: Total interconnect delay = 6.385 ns ( 78.16 % )" {  } {  } 0}  } { { "F:/DFF_REG/db/DFF_REG_cmp.qrpt" "" { Report "F:/DFF_REG/db/DFF_REG_cmp.qrpt" Compiler "DFF_REG" "UNKNOWN" "V1" "F:/DFF_REG/db/DFF_REG.quartus_db" { Floorplan "F:/DFF_REG/" "" "8.169 ns" { D Qi } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.169 ns" { D D~out0 Qi } { 0.000ns 0.000ns 6.385ns } { 0.000ns 1.475ns 0.309ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } {  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 4.241 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 4.241 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_G1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_G1; Fanout = 1; CLK Node = 'CLK'" {  } { { "F:/DFF_REG/db/DFF_REG_cmp.qrpt" "" { Report "F:/DFF_REG/db/DFF_REG_cmp.qrpt" Compiler "DFF_REG" "UNKNOWN" "V1" "F:/DFF_REG/db/DFF_REG.quartus_db" { Floorplan "F:/DFF_REG/" "" "" { CLK } "NODE_NAME" } "" } } { "DFF_REG.vhd" "" { Text "F:/DFF_REG/DFF_REG.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.061 ns) + CELL(0.711 ns) 4.241 ns Qi 2 REG LC_X1_Y16_N2 2 " "Info: 2: + IC(2.061 ns) + CELL(0.711 ns) = 4.241 ns; Loc. = LC_X1_Y16_N2; Fanout = 2; REG Node = 'Qi'" {  } { { "F:/DFF_REG/db/DFF_REG_cmp.qrpt" "" { Report "F:/DFF_REG/db/DFF_REG_cmp.qrpt" Compiler "DFF_REG" "UNKNOWN" "V1" "F:/DFF_REG/db/DFF_REG.quartus_db" { Floorplan "F:/DFF_REG/" "" "2.772 ns" { CLK Qi } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 51.40 % " "Info: Total cell delay = 2.180 ns ( 51.40 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.061 ns 48.60 % " "Info: Total interconnect delay = 2.061 ns ( 48.60 % )" {  } {  } 0}  } { { "F:/DFF_REG/db/DFF_REG_cmp.qrpt" "" { Report "F:/DFF_REG/db/DFF_REG_cmp.qrpt" Compiler "DFF_REG" "UNKNOWN" "V1" "F:/DFF_REG/db/DFF_REG.quartus_db" { Floorplan "F:/DFF_REG/" "" "4.241 ns" { CLK Qi } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.241 ns" { CLK CLK~out0 Qi } { 0.000ns 0.000ns 2.061ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "F:/DFF_REG/db/DFF_REG_cmp.qrpt" "" { Report "F:/DFF_REG/db/DFF_REG_cmp.qrpt" Compiler "DFF_REG" "UNKNOWN" "V1" "F:/DFF_REG/db/DFF_REG.quartus_db" { Floorplan "F:/DFF_REG/" "" "8.169 ns" { D Qi } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.169 ns" { D D~out0 Qi } { 0.000ns 0.000ns 6.385ns } { 0.000ns 1.475ns 0.309ns } } } { "F:/DFF_REG/db/DFF_REG_cmp.qrpt" "" { Report "F:/DFF_REG/db/DFF_REG_cmp.qrpt" Compiler "DFF_REG" "UNKNOWN" "V1" "F:/DFF_REG/db/DFF_REG.quartus_db" { Floorplan "F:/DFF_REG/" "" "4.241 ns" { CLK Qi } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.241 ns" { CLK CLK~out0 Qi } { 0.000ns 0.000ns 2.061ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK Q Qi 10.407 ns register " "Info: tco from clock \"CLK\" to destination pin \"Q\" through register \"Qi\" is 10.407 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 4.241 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 4.241 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_G1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_G1; Fanout = 1; CLK Node = 'CLK'" {  } { { "F:/DFF_REG/db/DFF_REG_cmp.qrpt" "" { Report "F:/DFF_REG/db/DFF_REG_cmp.qrpt" Compiler "DFF_REG" "UNKNOWN" "V1" "F:/DFF_REG/db/DFF_REG.quartus_db" { Floorplan "F:/DFF_REG/" "" "" { CLK } "NODE_NAME" } "" } } { "DFF_REG.vhd" "" { Text "F:/DFF_REG/DFF_REG.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.061 ns) + CELL(0.711 ns) 4.241 ns Qi 2 REG LC_X1_Y16_N2 2 " "Info: 2: + IC(2.061 ns) + CELL(0.711 ns) = 4.241 ns; Loc. = LC_X1_Y16_N2; Fanout = 2; REG Node = 'Qi'" {  } { { "F:/DFF_REG/db/DFF_REG_cmp.qrpt" "" { Report "F:/DFF_REG/db/DFF_REG_cmp.qrpt" Compiler "DFF_REG" "UNKNOWN" "V1" "F:/DFF_REG/db/DFF_REG.quartus_db" { Floorplan "F:/DFF_REG/" "" "2.772 ns" { CLK Qi } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 51.40 % " "Info: Total cell delay = 2.180 ns ( 51.40 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.061 ns 48.60 % " "Info: Total interconnect delay = 2.061 ns ( 48.60 % )" {  } {  } 0}  } { { "F:/DFF_REG/db/DFF_REG_cmp.qrpt" "" { Report "F:/DFF_REG/db/DFF_REG_cmp.qrpt" Compiler "DFF_REG" "UNKNOWN" "V1" "F:/DFF_REG/db/DFF_REG.quartus_db" { Floorplan "F:/DFF_REG/" "" "4.241 ns" { CLK Qi } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.241 ns" { CLK CLK~out0 Qi } { 0.000ns 0.000ns 2.061ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } {  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.942 ns + Longest register pin " "Info: + Longest register to pin delay is 5.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Qi 1 REG LC_X1_Y16_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y16_N2; Fanout = 2; REG Node = 'Qi'" {  } { { "F:/DFF_REG/db/DFF_REG_cmp.qrpt" "" { Report "F:/DFF_REG/db/DFF_REG_cmp.qrpt" Compiler "DFF_REG" "UNKNOWN" "V1" "F:/DFF_REG/db/DFF_REG.quartus_db" { Floorplan "F:/DFF_REG/" "" "" { Qi } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.834 ns) + CELL(2.108 ns) 5.942 ns Q 2 PIN PIN_B11 0 " "Info: 2: + IC(3.834 ns) + CELL(2.108 ns) = 5.942 ns; Loc. = PIN_B11; Fanout = 0; PIN Node = 'Q'" {  } { { "F:/DFF_REG/db/DFF_REG_cmp.qrpt" "" { Report "F:/DFF_REG/db/DFF_REG_cmp.qrpt" Compiler "DFF_REG" "UNKNOWN" "V1" "F:/DFF_REG/db/DFF_REG.quartus_db" { Floorplan "F:/DFF_REG/" "" "5.942 ns" { Qi Q } "NODE_NAME" } "" } } { "DFF_REG.vhd" "" { Text "F:/DFF_REG/DFF_REG.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns 35.48 % " "Info: Total cell delay = 2.108 ns ( 35.48 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.834 ns 64.52 % " "Info: Total interconnect delay = 3.834 ns ( 64.52 % )" {  } {  } 0}  } { { "F:/DFF_REG/db/DFF_REG_cmp.qrpt" "" { Report "F:/DFF_REG/db/DFF_REG_cmp.qrpt" Compiler "DFF_REG" "UNKNOWN" "V1" "F:/DFF_REG/db/DFF_REG.quartus_db" { Floorplan "F:/DFF_REG/" "" "5.942 ns" { Qi Q } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.942 ns" { Qi Q } { 0.000ns 3.834ns } { 0.000ns 2.108ns } } }  } 0}  } { { "F:/DFF_REG/db/DFF_REG_cmp.qrpt" "" { Report "F:/DFF_REG/db/DFF_REG_cmp.qrpt" Compiler "DFF_REG" "UNKNOWN" "V1" "F:/DFF_REG/db/DFF_REG.quartus_db" { Floorplan "F:/DFF_REG/" "" "4.241 ns" { CLK Qi } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.241 ns" { CLK CLK~out0 Qi } { 0.000ns 0.000ns 2.061ns } { 0.000ns 1.469ns 0.711ns } } } { "F:/DFF_REG/db/DFF_REG_cmp.qrpt" "" { Report "F:/DFF_REG/db/DFF_REG_cmp.qrpt" Compiler "DFF_REG" "UNKNOWN" "V1" "F:/DFF_REG/db/DFF_REG.quartus_db" { Floorplan "F:/DFF_REG/" "" "5.942 ns" { Qi Q } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.942 ns" { Qi Q } { 0.000ns 3.834ns } { 0.000ns 2.108ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "Qi D CLK -3.913 ns register " "Info: th for register \"Qi\" (data pin = \"D\", clock pin = \"CLK\") is -3.913 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 4.241 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 4.241 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_G1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_G1; Fanout = 1; CLK Node = 'CLK'" {  } { { "F:/DFF_REG/db/DFF_REG_cmp.qrpt" "" { Report "F:/DFF_REG/db/DFF_REG_cmp.qrpt" Compiler "DFF_REG" "UNKNOWN" "V1" "F:/DFF_REG/db/DFF_REG.quartus_db" { Floorplan "F:/DFF_REG/" "" "" { CLK } "NODE_NAME" } "" } } { "DFF_REG.vhd" "" { Text "F:/DFF_REG/DFF_REG.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.061 ns) + CELL(0.711 ns) 4.241 ns Qi 2 REG LC_X1_Y16_N2 2 " "Info: 2: + IC(2.061 ns) + CELL(0.711 ns) = 4.241 ns; Loc. = LC_X1_Y16_N2; Fanout = 2; REG Node = 'Qi'" {  } { { "F:/DFF_REG/db/DFF_REG_cmp.qrpt" "" { Report "F:/DFF_REG/db/DFF_REG_cmp.qrpt" Compiler "DFF_REG" "UNKNOWN" "V1" "F:/DFF_REG/db/DFF_REG.quartus_db" { Floorplan "F:/DFF_REG/" "" "2.772 ns" { CLK Qi } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 51.40 % " "Info: Total cell delay = 2.180 ns ( 51.40 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.061 ns 48.60 % " "Info: Total interconnect delay = 2.061 ns ( 48.60 % )" {  } {  } 0}  } { { "F:/DFF_REG/db/DFF_REG_cmp.qrpt" "" { Report "F:/DFF_REG/db/DFF_REG_cmp.qrpt" Compiler "DFF_REG" "UNKNOWN" "V1" "F:/DFF_REG/db/DFF_REG.quartus_db" { Floorplan "F:/DFF_REG/" "" "4.241 ns" { CLK Qi } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.241 ns" { CLK CLK~out0 Qi } { 0.000ns 0.000ns 2.061ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } {  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.169 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.169 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns D 1 PIN PIN_A6 1 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_A6; Fanout = 1; PIN Node = 'D'" {  } { { "F:/DFF_REG/db/DFF_REG_cmp.qrpt" "" { Report "F:/DFF_REG/db/DFF_REG_cmp.qrpt" Compiler "DFF_REG" "UNKNOWN" "V1" "F:/DFF_REG/db/DFF_REG.quartus_db" { Floorplan "F:/DFF_REG/" "" "" { D } "NODE_NAME" } "" } } { "DFF_REG.vhd" "" { Text "F:/DFF_REG/DFF_REG.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.385 ns) + CELL(0.309 ns) 8.169 ns Qi 2 REG LC_X1_Y16_N2 2 " "Info: 2: + IC(6.385 ns) + CELL(0.309 ns) = 8.169 ns; Loc. = LC_X1_Y16_N2; Fanout = 2; REG Node = 'Qi'" {  } { { "F:/DFF_REG/db/DFF_REG_cmp.qrpt" "" { Report "F:/DFF_REG/db/DFF_REG_cmp.qrpt" Compiler "DFF_REG" "UNKNOWN" "V1" "F:/DFF_REG/db/DFF_REG.quartus_db" { Floorplan "F:/DFF_REG/" "" "6.694 ns" { D Qi } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.784 ns 21.84 % " "Info: Total cell delay = 1.784 ns ( 21.84 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.385 ns 78.16 % " "Info: Total interconnect delay = 6.385 ns ( 78.16 % )" {  } {  } 0}  } { { "F:/DFF_REG/db/DFF_REG_cmp.qrpt" "" { Report "F:/DFF_REG/db/DFF_REG_cmp.qrpt" Compiler "DFF_REG" "UNKNOWN" "V1" "F:/DFF_REG/db/DFF_REG.quartus_db" { Floorplan "F:/DFF_REG/" "" "8.169 ns" { D Qi } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.169 ns" { D D~out0 Qi } { 0.000ns 0.000ns 6.385ns } { 0.000ns 1.475ns 0.309ns } } }  } 0}  } { { "F:/DFF_REG/db/DFF_REG_cmp.qrpt" "" { Report "F:/DFF_REG/db/DFF_REG_cmp.qrpt" Compiler "DFF_REG" "UNKNOWN" "V1" "F:/DFF_REG/db/DFF_REG.quartus_db" { Floorplan "F:/DFF_REG/" "" "4.241 ns" { CLK Qi } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.241 ns" { CLK CLK~out0 Qi } { 0.000ns 0.000ns 2.061ns } { 0.000ns 1.469ns 0.711ns } } } { "F:/DFF_REG/db/DFF_REG_cmp.qrpt" "" { Report "F:/DFF_REG/db/DFF_REG_cmp.qrpt" Compiler "DFF_REG" "UNKNOWN" "V1" "F:/DFF_REG/db/DFF_REG.quartus_db" { Floorplan "F:/DFF_REG/" "" "8.169 ns" { D Qi } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.169 ns" { D D~out0 Qi } { 0.000ns 0.000ns 6.385ns } { 0.000ns 1.475ns 0.309ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Jun 24 13:54:59 2006 " "Info: Processing ended: Sat Jun 24 13:54:59 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}