tlc5510.tan.qmsg

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

{ "Info" "ITDB_TH_RESULT" "DATA\[0\]~reg0 D\[0\] CLK 2.517 ns register " "Info: th for register \"DATA\[0\]~reg0\" (data pin = \"D\[0\]\", clock pin = \"CLK\") is 2.517 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 8.657 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 8.657 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_J1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J1; Fanout = 1; CLK Node = 'CLK'" {  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "" { CLK } "NODE_NAME" } "" } } { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.992 ns) + CELL(0.935 ns) 4.396 ns sta_G_CurrentState 2 REG LC_X8_Y10_N6 10 " "Info: 2: + IC(1.992 ns) + CELL(0.935 ns) = 4.396 ns; Loc. = LC_X8_Y10_N6; Fanout = 10; REG Node = 'sta_G_CurrentState'" {  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "2.927 ns" { CLK sta_G_CurrentState } "NODE_NAME" } "" } } { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.550 ns) + CELL(0.711 ns) 8.657 ns DATA\[0\]~reg0 3 REG LC_X1_Y20_N2 1 " "Info: 3: + IC(3.550 ns) + CELL(0.711 ns) = 8.657 ns; Loc. = LC_X1_Y20_N2; Fanout = 1; REG Node = 'DATA\[0\]~reg0'" {  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "4.261 ns" { sta_G_CurrentState DATA[0]~reg0 } "NODE_NAME" } "" } } { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 45 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 35.98 % " "Info: Total cell delay = 3.115 ns ( 35.98 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.542 ns 64.02 % " "Info: Total interconnect delay = 5.542 ns ( 64.02 % )" {  } {  } 0}  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "8.657 ns" { CLK sta_G_CurrentState DATA[0]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.657 ns" { CLK CLK~out0 sta_G_CurrentState DATA[0]~reg0 } { 0.000ns 0.000ns 1.992ns 3.550ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 45 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.155 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.155 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns D\[0\] 1 PIN PIN_D4 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_D4; Fanout = 1; PIN Node = 'D\[0\]'" {  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "" { D[0] } "NODE_NAME" } "" } } { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.571 ns) + CELL(0.115 ns) 6.155 ns DATA\[0\]~reg0 2 REG LC_X1_Y20_N2 1 " "Info: 2: + IC(4.571 ns) + CELL(0.115 ns) = 6.155 ns; Loc. = LC_X1_Y20_N2; Fanout = 1; REG Node = 'DATA\[0\]~reg0'" {  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "4.686 ns" { D[0] DATA[0]~reg0 } "NODE_NAME" } "" } } { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 45 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.584 ns 25.74 % " "Info: Total cell delay = 1.584 ns ( 25.74 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.571 ns 74.26 % " "Info: Total interconnect delay = 4.571 ns ( 74.26 % )" {  } {  } 0}  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "6.155 ns" { D[0] DATA[0]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.155 ns" { D[0] D[0]~out0 DATA[0]~reg0 } { 0.000ns 0.000ns 4.571ns } { 0.000ns 1.469ns 0.115ns } } }  } 0}  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "8.657 ns" { CLK sta_G_CurrentState DATA[0]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.657 ns" { CLK CLK~out0 sta_G_CurrentState DATA[0]~reg0 } { 0.000ns 0.000ns 1.992ns 3.550ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "6.155 ns" { D[0] DATA[0]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.155 ns" { D[0] D[0]~out0 DATA[0]~reg0 } { 0.000ns 0.000ns 4.571ns } { 0.000ns 1.469ns 0.115ns } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "CLK ADCLK sta_G_CurrentState 8.813 ns register " "Info: Minimum tco from clock \"CLK\" to destination pin \"ADCLK\" through register \"sta_G_CurrentState\" is 8.813 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 4.172 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to source register is 4.172 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_J1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J1; Fanout = 1; CLK Node = 'CLK'" {  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "" { CLK } "NODE_NAME" } "" } } { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.992 ns) + CELL(0.711 ns) 4.172 ns sta_G_CurrentState 2 REG LC_X8_Y10_N6 10 " "Info: 2: + IC(1.992 ns) + CELL(0.711 ns) = 4.172 ns; Loc. = LC_X8_Y10_N6; Fanout = 10; REG Node = 'sta_G_CurrentState'" {  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "2.703 ns" { CLK sta_G_CurrentState } "NODE_NAME" } "" } } { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 52.25 % " "Info: Total cell delay = 2.180 ns ( 52.25 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.992 ns 47.75 % " "Info: Total interconnect delay = 1.992 ns ( 47.75 % )" {  } {  } 0}  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "4.172 ns" { CLK sta_G_CurrentState } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.172 ns" { CLK CLK~out0 sta_G_CurrentState } { 0.0ns 0.0ns 1.992ns } { 0.0ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.417 ns + Shortest register pin " "Info: + Shortest register to pin delay is 4.417 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sta_G_CurrentState 1 REG LC_X8_Y10_N6 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y10_N6; Fanout = 10; REG Node = 'sta_G_CurrentState'" {  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "" { sta_G_CurrentState } "NODE_NAME" } "" } } { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.309 ns) + CELL(2.108 ns) 4.417 ns ADCLK 2 PIN PIN_M6 0 " "Info: 2: + IC(2.309 ns) + CELL(2.108 ns) = 4.417 ns; Loc. = PIN_M6; Fanout = 0; PIN Node = 'ADCLK'" {  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "4.417 ns" { sta_G_CurrentState ADCLK } "NODE_NAME" } "" } } { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns 47.72 % " "Info: Total cell delay = 2.108 ns ( 47.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.309 ns 52.28 % " "Info: Total interconnect delay = 2.309 ns ( 52.28 % )" {  } {  } 0}  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "4.417 ns" { sta_G_CurrentState ADCLK } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.417 ns" { sta_G_CurrentState ADCLK } { 0.0ns 2.309ns } { 0.0ns 2.108ns } } }  } 0}  } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "4.172 ns" { CLK sta_G_CurrentState } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.172 ns" { CLK CLK~out0 sta_G_CurrentState } { 0.0ns 0.0ns 1.992ns } { 0.0ns 1.469ns 0.711ns } } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "4.417 ns" { sta_G_CurrentState ADCLK } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.417 ns" { sta_G_CurrentState ADCLK } { 0.0ns 2.309ns } { 0.0ns 2.108ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Jun 25 22:22:23 2006 " "Info: Processing ended: Sun Jun 25 22:22:23 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}