📄 tlc5510.tan.qmsg
字号:
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "sta_G_CurrentState " "Info: Detected ripple clock \"sta_G_CurrentState\" as buffer" { } { { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 18 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sta_G_CurrentState" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLK register register sta_G_CurrentState sta_G_CurrentState 275.03 MHz Internal " "Info: Clock \"CLK\" Internal fmax is restricted to 275.03 MHz between source register \"sta_G_CurrentState\" and destination register \"sta_G_CurrentState\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.823 ns + Longest register register " "Info: + Longest register to register delay is 0.823 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sta_G_CurrentState 1 REG LC_X8_Y10_N6 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y10_N6; Fanout = 10; REG Node = 'sta_G_CurrentState'" { } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "" { sta_G_CurrentState } "NODE_NAME" } "" } } { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 18 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.514 ns) + CELL(0.309 ns) 0.823 ns sta_G_CurrentState 2 REG LC_X8_Y10_N6 10 " "Info: 2: + IC(0.514 ns) + CELL(0.309 ns) = 0.823 ns; Loc. = LC_X8_Y10_N6; Fanout = 10; REG Node = 'sta_G_CurrentState'" { } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "0.823 ns" { sta_G_CurrentState sta_G_CurrentState } "NODE_NAME" } "" } } { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 18 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns 37.55 % " "Info: Total cell delay = 0.309 ns ( 37.55 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.514 ns 62.45 % " "Info: Total interconnect delay = 0.514 ns ( 62.45 % )" { } { } 0} } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "0.823 ns" { sta_G_CurrentState sta_G_CurrentState } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "0.823 ns" { sta_G_CurrentState sta_G_CurrentState } { 0.000ns 0.514ns } { 0.000ns 0.309ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 4.172 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 4.172 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_J1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J1; Fanout = 1; CLK Node = 'CLK'" { } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "" { CLK } "NODE_NAME" } "" } } { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.992 ns) + CELL(0.711 ns) 4.172 ns sta_G_CurrentState 2 REG LC_X8_Y10_N6 10 " "Info: 2: + IC(1.992 ns) + CELL(0.711 ns) = 4.172 ns; Loc. = LC_X8_Y10_N6; Fanout = 10; REG Node = 'sta_G_CurrentState'" { } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "2.703 ns" { CLK sta_G_CurrentState } "NODE_NAME" } "" } } { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 18 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 52.25 % " "Info: Total cell delay = 2.180 ns ( 52.25 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.992 ns 47.75 % " "Info: Total interconnect delay = 1.992 ns ( 47.75 % )" { } { } 0} } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "4.172 ns" { CLK sta_G_CurrentState } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.172 ns" { CLK CLK~out0 sta_G_CurrentState } { 0.000ns 0.000ns 1.992ns } { 0.000ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 4.172 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 4.172 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_J1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J1; Fanout = 1; CLK Node = 'CLK'" { } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "" { CLK } "NODE_NAME" } "" } } { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.992 ns) + CELL(0.711 ns) 4.172 ns sta_G_CurrentState 2 REG LC_X8_Y10_N6 10 " "Info: 2: + IC(1.992 ns) + CELL(0.711 ns) = 4.172 ns; Loc. = LC_X8_Y10_N6; Fanout = 10; REG Node = 'sta_G_CurrentState'" { } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "2.703 ns" { CLK sta_G_CurrentState } "NODE_NAME" } "" } } { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 18 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 52.25 % " "Info: Total cell delay = 2.180 ns ( 52.25 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.992 ns 47.75 % " "Info: Total interconnect delay = 1.992 ns ( 47.75 % )" { } { } 0} } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "4.172 ns" { CLK sta_G_CurrentState } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.172 ns" { CLK CLK~out0 sta_G_CurrentState } { 0.000ns 0.000ns 1.992ns } { 0.000ns 1.469ns 0.711ns } } } } 0} } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "4.172 ns" { CLK sta_G_CurrentState } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.172 ns" { CLK CLK~out0 sta_G_CurrentState } { 0.000ns 0.000ns 1.992ns } { 0.000ns 1.469ns 0.711ns } } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "4.172 ns" { CLK sta_G_CurrentState } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.172 ns" { CLK CLK~out0 sta_G_CurrentState } { 0.000ns 0.000ns 1.992ns } { 0.000ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 18 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 18 -1 0 } } } 0} } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "0.823 ns" { sta_G_CurrentState sta_G_CurrentState } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "0.823 ns" { sta_G_CurrentState sta_G_CurrentState } { 0.000ns 0.514ns } { 0.000ns 0.309ns } } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "4.172 ns" { CLK sta_G_CurrentState } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.172 ns" { CLK CLK~out0 sta_G_CurrentState } { 0.000ns 0.000ns 1.992ns } { 0.000ns 1.469ns 0.711ns } } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "4.172 ns" { CLK sta_G_CurrentState } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.172 ns" { CLK CLK~out0 sta_G_CurrentState } { 0.000ns 0.000ns 1.992ns } { 0.000ns 1.469ns 0.711ns } } } } 0} } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "" { sta_G_CurrentState } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { sta_G_CurrentState } { } { } } } { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 18 -1 0 } } } 0}
{ "Info" "ITDB_TSU_RESULT" "DATA\[6\]~reg0 D\[6\] CLK -1.782 ns register " "Info: tsu for register \"DATA\[6\]~reg0\" (data pin = \"D\[6\]\", clock pin = \"CLK\") is -1.782 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.788 ns + Longest pin register " "Info: + Longest pin to register delay is 6.788 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns D\[6\] 1 PIN PIN_R8 1 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_R8; Fanout = 1; PIN Node = 'D\[6\]'" { } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "" { D[6] } "NODE_NAME" } "" } } { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.004 ns) + CELL(0.309 ns) 6.788 ns DATA\[6\]~reg0 2 REG LC_X12_Y1_N2 1 " "Info: 2: + IC(5.004 ns) + CELL(0.309 ns) = 6.788 ns; Loc. = LC_X12_Y1_N2; Fanout = 1; REG Node = 'DATA\[6\]~reg0'" { } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "5.313 ns" { D[6] DATA[6]~reg0 } "NODE_NAME" } "" } } { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 45 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.784 ns 26.28 % " "Info: Total cell delay = 1.784 ns ( 26.28 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.004 ns 73.72 % " "Info: Total interconnect delay = 5.004 ns ( 73.72 % )" { } { } 0} } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "6.788 ns" { D[6] DATA[6]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.788 ns" { D[6] D[6]~out0 DATA[6]~reg0 } { 0.000ns 0.000ns 5.004ns } { 0.000ns 1.475ns 0.309ns } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 45 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 8.607 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 8.607 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_J1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J1; Fanout = 1; CLK Node = 'CLK'" { } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "" { CLK } "NODE_NAME" } "" } } { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.992 ns) + CELL(0.935 ns) 4.396 ns sta_G_CurrentState 2 REG LC_X8_Y10_N6 10 " "Info: 2: + IC(1.992 ns) + CELL(0.935 ns) = 4.396 ns; Loc. = LC_X8_Y10_N6; Fanout = 10; REG Node = 'sta_G_CurrentState'" { } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "2.927 ns" { CLK sta_G_CurrentState } "NODE_NAME" } "" } } { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 18 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.500 ns) + CELL(0.711 ns) 8.607 ns DATA\[6\]~reg0 3 REG LC_X12_Y1_N2 1 " "Info: 3: + IC(3.500 ns) + CELL(0.711 ns) = 8.607 ns; Loc. = LC_X12_Y1_N2; Fanout = 1; REG Node = 'DATA\[6\]~reg0'" { } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "4.211 ns" { sta_G_CurrentState DATA[6]~reg0 } "NODE_NAME" } "" } } { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 45 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 36.19 % " "Info: Total cell delay = 3.115 ns ( 36.19 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.492 ns 63.81 % " "Info: Total interconnect delay = 5.492 ns ( 63.81 % )" { } { } 0} } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "8.607 ns" { CLK sta_G_CurrentState DATA[6]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.607 ns" { CLK CLK~out0 sta_G_CurrentState DATA[6]~reg0 } { 0.000ns 0.000ns 1.992ns 3.500ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } } 0} } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "6.788 ns" { D[6] DATA[6]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.788 ns" { D[6] D[6]~out0 DATA[6]~reg0 } { 0.000ns 0.000ns 5.004ns } { 0.000ns 1.475ns 0.309ns } } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "8.607 ns" { CLK sta_G_CurrentState DATA[6]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.607 ns" { CLK CLK~out0 sta_G_CurrentState DATA[6]~reg0 } { 0.000ns 0.000ns 1.992ns 3.500ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK DATA\[2\] DATA\[2\]~reg0 12.345 ns register " "Info: tco from clock \"CLK\" to destination pin \"DATA\[2\]\" through register \"DATA\[2\]~reg0\" is 12.345 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 8.666 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 8.666 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_J1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_J1; Fanout = 1; CLK Node = 'CLK'" { } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "" { CLK } "NODE_NAME" } "" } } { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.992 ns) + CELL(0.935 ns) 4.396 ns sta_G_CurrentState 2 REG LC_X8_Y10_N6 10 " "Info: 2: + IC(1.992 ns) + CELL(0.935 ns) = 4.396 ns; Loc. = LC_X8_Y10_N6; Fanout = 10; REG Node = 'sta_G_CurrentState'" { } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "2.927 ns" { CLK sta_G_CurrentState } "NODE_NAME" } "" } } { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 18 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.559 ns) + CELL(0.711 ns) 8.666 ns DATA\[2\]~reg0 3 REG LC_X26_Y19_N2 1 " "Info: 3: + IC(3.559 ns) + CELL(0.711 ns) = 8.666 ns; Loc. = LC_X26_Y19_N2; Fanout = 1; REG Node = 'DATA\[2\]~reg0'" { } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "4.270 ns" { sta_G_CurrentState DATA[2]~reg0 } "NODE_NAME" } "" } } { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 45 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 35.95 % " "Info: Total cell delay = 3.115 ns ( 35.95 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.551 ns 64.05 % " "Info: Total interconnect delay = 5.551 ns ( 64.05 % )" { } { } 0} } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "8.666 ns" { CLK sta_G_CurrentState DATA[2]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.666 ns" { CLK CLK~out0 sta_G_CurrentState DATA[2]~reg0 } { 0.000ns 0.000ns 1.992ns 3.559ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 45 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.455 ns + Longest register pin " "Info: + Longest register to pin delay is 3.455 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DATA\[2\]~reg0 1 REG LC_X26_Y19_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y19_N2; Fanout = 1; REG Node = 'DATA\[2\]~reg0'" { } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "" { DATA[2]~reg0 } "NODE_NAME" } "" } } { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 45 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.347 ns) + CELL(2.108 ns) 3.455 ns DATA\[2\] 2 PIN PIN_D11 0 " "Info: 2: + IC(1.347 ns) + CELL(2.108 ns) = 3.455 ns; Loc. = PIN_D11; Fanout = 0; PIN Node = 'DATA\[2\]'" { } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "3.455 ns" { DATA[2]~reg0 DATA[2] } "NODE_NAME" } "" } } { "TLC5510.vhd" "" { Text "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/TLC5510.vhd" 9 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns 61.01 % " "Info: Total cell delay = 2.108 ns ( 61.01 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.347 ns 38.99 % " "Info: Total interconnect delay = 1.347 ns ( 38.99 % )" { } { } 0} } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "3.455 ns" { DATA[2]~reg0 DATA[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.455 ns" { DATA[2]~reg0 DATA[2] } { 0.000ns 1.347ns } { 0.000ns 2.108ns } } } } 0} } { { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "8.666 ns" { CLK sta_G_CurrentState DATA[2]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.666 ns" { CLK CLK~out0 sta_G_CurrentState DATA[2]~reg0 } { 0.000ns 0.000ns 1.992ns 3.559ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" "" { Report "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510_cmp.qrpt" Compiler "TLC5510" "UNKNOWN" "V1" "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/db/TLC5510.quartus_db" { Floorplan "F:/可编成逻辑设计软件Quartus II/project\[04\]/TLC5510/" "" "3.455 ns" { DATA[2]~reg0 DATA[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.455 ns" { DATA[2]~reg0 DATA[2] } { 0.000ns 1.347ns } { 0.000ns 2.108ns } } } } 0}
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -