standard.tan.rpt

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; fmax Requirement                                      ; 55.0 MHz           ;      ;    ;             ;
; Ignore Clock Settings                                 ; On                 ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                            ;
+-------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                           ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+-------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; PLL:inst|altpll:altpll_component|_clk0    ;                    ; PLL output ; 48.0 MHz         ; 0.000 ns      ; 0.000 ns     ; SYS_CLK  ; 1                     ; 1                   ; -1.885 ns ;              ;
; PLL:inst|altpll:altpll_component|_extclk0 ;                    ; PLL output ; 48.0 MHz         ; 0.000 ns      ; 0.000 ns     ; SYS_CLK  ; 1                     ; 1                   ; -1.885 ns ;              ;
; SYS_CLK                                   ;                    ; User Pin   ; 48.0 MHz         ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A       ;              ;
; altera_internal_jtag~TCKUTAP              ;                    ; User Pin   ; 55.0 MHz         ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A       ;              ;
; altera_internal_jtag~UPDATEUSER           ;                    ; User Pin   ; 55.0 MHz         ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A       ;              ;
+-------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'PLL:inst|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------+----------------------------------------+----------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                               ; To                                                                                                                         ; From Clock                             ; To Clock                               ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------+----------------------------------------+----------------------------------------+-----------------------------+---------------------------+-------------------------+
; 0.335 ns                                ; 48.79 MHz ( period = 20.498 ns )                    ; standard_1c6:inst3|cpu_0:the_cpu_0|ic_fill_tag[14]                                                                                                 ; standard_1c6:inst3|ext_mem_bus_avalon_slave_arbitrator:the_ext_mem_bus_avalon_slave|ext_mem_bus_address[17]                ; PLL:inst|altpll:altpll_component|_clk0 ; PLL:inst|altpll:altpll_component|_clk0 ; 20.833 ns                   ; 19.803 ns                 ; 19.468 ns               ;
; 0.471 ns                                ; 49.11 MHz ( period = 20.362 ns )                    ; standard_1c6:inst3|cpu_0:the_cpu_0|ic_fill_tag[15]                                                                                                 ; standard_1c6:inst3|ext_mem_bus_avalon_slave_arbitrator:the_ext_mem_bus_avalon_slave|ext_mem_bus_address[17]                ; PLL:inst|altpll:altpll_component|_clk0 ; PLL:inst|altpll:altpll_component|_clk0 ; 20.833 ns                   ; 19.803 ns                 ; 19.332 ns               ;
; 0.503 ns                                ; 49.19 MHz ( period = 20.330 ns )                    ; standard_1c6:inst3|cpu_0:the_cpu_0|ic_fill_tag[14]                                                                                                 ; standard_1c6:inst3|ext_mem_bus_avalon_slave_arbitrator:the_ext_mem_bus_avalon_slave|ext_mem_bus_address[4]                 ; PLL:inst|altpll:altpll_component|_clk0 ; PLL:inst|altpll:altpll_component|_clk0 ; 20.833 ns                   ; 19.803 ns                 ; 19.300 ns               ;
; 0.516 ns                                ; 49.22 MHz ( period = 20.317 ns )                    ; standard_1c6:inst3|cpu_0:the_cpu_0|ic_fill_tag[14]                                                                                                 ; standard_1c6:inst3|ext_mem_bus_avalon_slave_arbitrator:the_ext_mem_bus_avalon_slave|ext_mem_bus_address[23]                ; PLL:inst|altpll:altpll_component|_clk0 ; PLL:inst|altpll:altpll_component|_clk0 ; 20.833 ns                   ; 19.803 ns                 ; 19.287 ns               ;
; 0.639 ns                                ; 49.52 MHz ( period = 20.194 ns )                    ; standard_1c6:inst3|cpu_0:the_cpu_0|ic_fill_tag[15]                                                                                                 ; standard_1c6:inst3|ext_mem_bus_avalon_slave_arbitrator:the_ext_mem_bus_avalon_slave|ext_mem_bus_address[4]                 ; PLL:inst|altpll:altpll_component|_clk0 ; PLL:inst|altpll:altpll_component|_clk0 ; 20.833 ns                   ; 19.803 ns                 ; 19.164 ns               ;
; 0.652 ns                                ; 49.55 MHz ( period = 20.181 ns )                    ; standard_1c6:inst3|cpu_0:the_cpu_0|ic_fill_tag[15]                                                                                                 ; standard_1c6:inst3|ext_mem_bus_avalon_slave_arbitrator:the_ext_mem_bus_avalon_slave|ext_mem_bus_address[23]                ; PLL:inst|altpll:altpll_component|_clk0 ; PLL:inst|altpll:altpll_component|_clk0 ; 20.833 ns                   ; 19.803 ns                 ; 19.151 ns               ;
; 0.698 ns                                ; 49.66 MHz ( period = 20.135 ns )                    ; standard_1c6:inst3|cpu_0:the_cpu_0|ic_fill_tag[2]                                                                                                  ; standard_1c6:inst3|ext_mem_bus_avalon_slave_arbitrator:the_ext_mem_bus_avalon_slave|ext_mem_bus_address[17]                ; PLL:inst|altpll:altpll_component|_clk0 ; PLL:inst|altpll:altpll_component|_clk0 ; 20.833 ns                   ; 19.803 ns                 ; 19.105 ns               ;