standard.tan.rpt

来自「郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程」· RPT 代码 · 共 198 行 · 第 1/5 页

Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+-------------------------------------------------------+-----------+----------------------------------+----------------------------------+------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+----------------------------------------+--------------+
; Type                                                  ; Slack     ; Required Time                    ; Actual Time                      ; From                                                                                                                               ; To                                                                                                                                                                                                         ; From Clock                             ; To Clock                               ; Failed Paths ;
+-------------------------------------------------------+-----------+----------------------------------+----------------------------------+------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+----------------------------------------+--------------+
; Worst-case tsu                                        ; N/A       ; None                             ; 9.339 ns                         ; P0[26]                                                                                                                             ; standard_1c6:inst3|p0_7_p0_30:the_p0_7_p0_30|readdata[19]                                                                                                                                                  ;                                        ; SYS_CLK                                ; 0            ;
; Worst-case tco                                        ; N/A       ; None                             ; 9.826 ns                         ; standard_1c6:inst3|ext_mem_bus_avalon_slave_arbitrator:the_ext_mem_bus_avalon_slave|select_n_to_the_S1D13503_Register~_Duplicate_1 ; Ext_Bus_nEN                                                                                                                                                                                                ; SYS_CLK                                ;                                        ; 0            ;
; Worst-case tpd                                        ; N/A       ; None                             ; 10.144 ns                        ; NF_nBUSY                                                                                                                           ; NF_nCS                                                                                                                                                                                                     ;                                        ;                                        ; 0            ;
; Worst-case th                                         ; N/A       ; None                             ; 1.166 ns                         ; altera_internal_jtag~SHIFTUSER                                                                                                     ; standard_1c6:inst3|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|st_shiftdr ;                                        ; altera_internal_jtag~TCKUTAP           ; 0            ;
; Worst-case Minimum tco                                ; N/A       ; None                             ; 0.924 ns                         ; PLL:inst|altpll:altpll_component|_extclk0                                                                                          ; SDRAM_CLK                                                                                                                                                                                                  ; SYS_CLK                                ;                                        ; 0            ;
; Worst-case Minimum tpd                                ; N/A       ; None                             ; 2.124 ns                         ; altera_internal_jtag~TDO                                                                                                           ; altera_reserved_tdo                                                                                                                                                                                        ;                                        ;                                        ; 0            ;
; Clock Setup: 'PLL:inst|altpll:altpll_component|_clk0' ; 0.335 ns  ; 48.00 MHz ( period = 20.833 ns ) ; 48.79 MHz ( period = 20.498 ns ) ; standard_1c6:inst3|cpu_0:the_cpu_0|ic_fill_tag[14]                                                                                 ; standard_1c6:inst3|ext_mem_bus_avalon_slave_arbitrator:the_ext_mem_bus_avalon_slave|ext_mem_bus_address[17]                                                                                                ; PLL:inst|altpll:altpll_component|_clk0 ; PLL:inst|altpll:altpll_component|_clk0 ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP'           ; 4.852 ns  ; 55.00 MHz ( period = 18.181 ns ) ; 117.98 MHz ( period = 8.476 ns ) ; sld_hub:sld_hub_inst|jtag_debug_mode                                                                                               ; standard_1c6:inst3|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|jupdate                                                                                                           ; altera_internal_jtag~TCKUTAP           ; altera_internal_jtag~TCKUTAP           ; 0            ;
; Clock Setup: 'SYS_CLK'                                ; 16.062 ns ; 48.00 MHz ( period = 20.833 ns ) ; 209.60 MHz ( period = 4.771 ns ) ; delay_reset_block:inst6|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_df8:auto_generated|safe_q[0]                     ; delay_reset_block:inst6|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_df8:auto_generated|safe_q[0]                                                                                             ; SYS_CLK                                ; SYS_CLK                                ; 0            ;
; Clock Hold: 'PLL:inst|altpll:altpll_component|_clk0'  ; 0.822 ns  ; 48.00 MHz ( period = 20.833 ns ) ; N/A                              ; standard_1c6:inst3|cpu_0:the_cpu_0|ic_fill_dp_offset[1]                                                                            ; standard_1c6:inst3|cpu_0:the_cpu_0|ic_fill_dp_offset[1]                                                                                                                                                    ; PLL:inst|altpll:altpll_component|_clk0 ; PLL:inst|altpll:altpll_component|_clk0 ; 0            ;
; Clock Hold: 'altera_internal_jtag~TCKUTAP'            ; 0.871 ns  ; 55.00 MHz ( period = 18.181 ns ) ; N/A                              ; sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[1]                                                                            ; sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0]                                                                                                                                                    ; altera_internal_jtag~TCKUTAP           ; altera_internal_jtag~TCKUTAP           ; 0            ;
; Clock Hold: 'SYS_CLK'                                 ; 1.314 ns  ; 48.00 MHz ( period = 20.833 ns ) ; N/A                              ; delay_reset_block:inst6|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_df8:auto_generated|safe_q[9]                     ; delay_reset_block:inst6|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_df8:auto_generated|safe_q[9]                                                                                             ; SYS_CLK                                ; SYS_CLK                                ; 0            ;
; Total number of failed paths                          ;           ;                                  ;                                  ;                                                                                                                                    ;                                                                                                                                                                                                            ;                                        ;                                        ; 0            ;
+-------------------------------------------------------+-----------+----------------------------------+----------------------------------+------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+----------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C6F256C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; On                 ;      ;    ;             ;