addere.srr

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

#Program: Synplify Pro 8.1
#OS: Windows_NT

$ Start of Compile
#Sun Mar 26 12:20:53 2006

Synplicity VHDL Compiler, version 3.1.0, Build 049R, built May  3 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved

VHDL syntax check successful!
Options changed - recompiling
@N:"E:\QProj\AdderE syn\AdderE.vhd":2:7:2:12|Synthesizing work.addere.syn 
@N:"E:\QProj\AdderE syn\Full_Adder.vhd":2:7:2:16|Synthesizing work.full_adder.syn 
Post processing for work.full_adder.syn
Post processing for work.addere.syn
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sun Mar 26 12:20:54 2006

###########################################################[
Version 8.1
Synplicity Altera Technology Mapper, Version 8.1.0, Build 539R, Built May  6 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved


@N: MT204 |Autoconstrain Mode is ON
@N|Only System clock will be Autoconstrained
RTL optimization done.
@N: MF197 |Retiming summary : 0 registers retimed to 0 

		#####  BEGIN RETIMING REPORT  #####

Retiming summary : 0 registers retimed to 0

Original and Pipelined registers replaced by retiming :
		None

New registers created by retiming :
		None


		#####   END RETIMING REPORT  #####


Writing Analyst data base E:\QProj\AdderE syn\rev_1\AdderE.srm
Writing Verilog Netlist and constraint files
Writing .vqm output for Quartus
Writing Cross reference file for Quartus to E:\QProj\AdderE syn\rev_1\AdderE.xrf


##### START OF TIMING REPORT #####[
# Timing Report written on Sun Mar 26 12:20:58 2006
#


Top view:               AdderE
Requested Frequency:    1.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT197 |Clock constraints cover only FF-to-FF paths associated with the clock..



Performance Summary 
*******************


Worst slack in design: NA






Interface Information 
*********************

		No IO constraint found 


##### END OF TIMING REPORT #####]

##### START OF AREA REPORT #####[
Design view:work.AdderE(syn)
Selecting part EP1C6F256C8
@N: FA174 |The following device usage report estimates place and route data. Please look at the place and route report for final resource usage..

I/O ATOMs:       26

Total LUTs:  16 of 5980 ( 0%)
Logic resources:  16 ATOMs of 5980 ( 0%)
ATOM count by mode:
  normal:       16
  arithmetic:   0

ShiftTap:       0  (0 registers)
Total ESB:      0 bits   (0% of 81920)

ATOMs using regout pin: 0
  also using enable pin: 0
  also using combout pin: 0
ATOMs using combout pin: 16
Number of Inputs on ATOMs: 48
Number of Nets:   117

##### END OF AREA REPORT #####]

Mapper successful!
Process took 0h:0m:3s realtime, 0h:0m:3s cputime
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