addere.vqm

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

//
// Written by Synplify
// Synplify 7.7.0, Build 054R.
// Thu May 04 11:26:58 2006
//
// Source file index table:
// Object locations will have the form <file>:<line>
// file 0 "noname"
// file 1 "\d:\synplicity\synplify_771\lib\vhd\std.vhd "
// file 2 "\e:\qproj\addere\full_adder.vhd "
// file 3 "\e:\qproj\addere\addere.vhd "

module Full_Adder (
  B_c_0,
  A_c_0,
  SUM,
  CIN_c,
  COUT
);
input B_c_0 ;
input A_c_0 ;
output SUM ;
input CIN_c ;
output COUT ;
wire B_c_0 ;
wire A_c_0 ;
wire SUM ;
wire CIN_c ;
wire COUT ;
wire GND ;
wire VCC ;
  assign VCC = 1'b1;
  assign GND = 1'b0;
// @2:16
  cyclone_lcell COUT_0 (
	.combout(COUT),
	.dataa(A_c_0),
	.datab(B_c_0),
	.datac(CIN_c)
);
defparam COUT_0.operation_mode="normal";
defparam COUT_0.output_mode="comb_only";
defparam COUT_0.lut_mask="1717";
defparam COUT_0.synch_mode="off";
defparam COUT_0.sum_lutc_input="datac";
// @2:15
  cyclone_lcell SUM_0 (
	.combout(SUM),
	.dataa(A_c_0),
	.datab(B_c_0),
	.datac(CIN_c)
);
defparam SUM_0.operation_mode="normal";
defparam SUM_0.output_mode="comb_only";
defparam SUM_0.lut_mask="9696";
defparam SUM_0.synch_mode="off";
defparam SUM_0.sum_lutc_input="datac";
endmodule /* Full_Adder */

module Full_Adder_1 (
  B_c_0,
  A_c_0,
  SUM,
  COUT_0,
  COUT
);
input B_c_0 ;
input A_c_0 ;
output SUM ;
input COUT_0 ;
output COUT ;
wire B_c_0 ;
wire A_c_0 ;
wire SUM ;
wire COUT_0 ;
wire COUT ;
wire GND ;
wire VCC ;
  assign VCC = 1'b1;
  assign GND = 1'b0;
// @2:16
  cyclone_lcell COUT_1 (
	.combout(COUT),
	.dataa(A_c_0),
	.datab(B_c_0),
	.datac(COUT_0)
);
defparam COUT_1.operation_mode="normal";
defparam COUT_1.output_mode="comb_only";
defparam COUT_1.lut_mask="7171";
defparam COUT_1.synch_mode="off";
defparam COUT_1.sum_lutc_input="datac";
// @2:15
  cyclone_lcell SUM_0 (
	.combout(SUM),
	.dataa(A_c_0),
	.datab(B_c_0),
	.datac(COUT_0)
);
defparam SUM_0.operation_mode="normal";
defparam SUM_0.output_mode="comb_only";
defparam SUM_0.lut_mask="6969";
defparam SUM_0.synch_mode="off";
defparam SUM_0.sum_lutc_input="datac";
endmodule /* Full_Adder_1 */

module Full_Adder_2 (
  B_c_0,
  A_c_0,
  SUM,
  COUT_0,
  COUT
);
input B_c_0 ;
input A_c_0 ;
output SUM ;
input COUT_0 ;
output COUT ;
wire B_c_0 ;
wire A_c_0 ;
wire SUM ;
wire COUT_0 ;
wire COUT ;
wire GND ;
wire VCC ;
  assign VCC = 1'b1;
  assign GND = 1'b0;
// @2:16
  cyclone_lcell COUT_1 (
	.combout(COUT),
	.dataa(A_c_0),
	.datab(B_c_0),
	.datac(COUT_0)
);
defparam COUT_1.operation_mode="normal";
defparam COUT_1.output_mode="comb_only";
defparam COUT_1.lut_mask="7171";
defparam COUT_1.synch_mode="off";
defparam COUT_1.sum_lutc_input="datac";
// @2:15
  cyclone_lcell SUM_0 (
	.combout(SUM),
	.dataa(A_c_0),
	.datab(B_c_0),
	.datac(COUT_0)
);
defparam SUM_0.operation_mode="normal";
defparam SUM_0.output_mode="comb_only";
defparam SUM_0.lut_mask="6969";
defparam SUM_0.synch_mode="off";
defparam SUM_0.sum_lutc_input="datac";
endmodule /* Full_Adder_2 */

module Full_Adder_3 (
  B_c_0,
  A_c_0,
  SUM,
  COUT,
  N_5_i
);
input B_c_0 ;
input A_c_0 ;
output SUM ;
input COUT ;
output N_5_i ;
wire B_c_0 ;
wire A_c_0 ;
wire SUM ;
wire COUT ;
wire N_5_i ;
wire GND ;
wire VCC ;
  assign VCC = 1'b1;
  assign GND = 1'b0;
// @2:16
  cyclone_lcell COUT_0 (
	.combout(N_5_i),
	.dataa(A_c_0),
	.datab(B_c_0),
	.datac(COUT)
);
defparam COUT_0.operation_mode="normal";
defparam COUT_0.output_mode="comb_only";
defparam COUT_0.lut_mask="8e8e";
defparam COUT_0.synch_mode="off";
defparam COUT_0.sum_lutc_input="datac";
// @2:15
  cyclone_lcell SUM_0 (
	.combout(SUM),
	.dataa(A_c_0),
	.datab(B_c_0),
	.datac(COUT)
);
defparam SUM_0.operation_mode="normal";
defparam SUM_0.output_mode="comb_only";
defparam SUM_0.lut_mask="6969";
defparam SUM_0.synch_mode="off";
defparam SUM_0.sum_lutc_input="datac";
endmodule /* Full_Adder_3 */

module Full_Adder_4 (
  B_c_0,
  A_c_0,
  SUM,
  COUT_0,
  COUT
);
input B_c_0 ;
input A_c_0 ;
output SUM ;
input COUT_0 ;
output COUT ;
wire B_c_0 ;
wire A_c_0 ;
wire SUM ;
wire COUT_0 ;
wire COUT ;
wire GND ;
wire VCC ;
  assign VCC = 1'b1;
  assign GND = 1'b0;
// @2:16
  cyclone_lcell COUT_1 (
	.combout(COUT),
	.dataa(A_c_0),
	.datab(B_c_0),
	.datac(COUT_0)
);
defparam COUT_1.operation_mode="normal";
defparam COUT_1.output_mode="comb_only";
defparam COUT_1.lut_mask="7171";
defparam COUT_1.synch_mode="off";
defparam COUT_1.sum_lutc_input="datac";
// @2:15
  cyclone_lcell SUM_0 (
	.combout(SUM),
	.dataa(A_c_0),
	.datab(B_c_0),
	.datac(COUT_0)
);
defparam SUM_0.operation_mode="normal";
defparam SUM_0.output_mode="comb_only";
defparam SUM_0.lut_mask="6969";
defparam SUM_0.synch_mode="off";
defparam SUM_0.sum_lutc_input="datac";
endmodule /* Full_Adder_4 */

module Full_Adder_5 (
  B_c_0,
  A_c_0,
  SUM,
  COUT_0,
  COUT
);
input B_c_0 ;
input A_c_0 ;
output SUM ;
input COUT_0 ;
output COUT ;
wire B_c_0 ;
wire A_c_0 ;
wire SUM ;
wire COUT_0 ;
wire COUT ;
wire GND ;
wire VCC ;
  assign VCC = 1'b1;
  assign GND = 1'b0;
// @2:16
  cyclone_lcell COUT_1 (
	.combout(COUT),
	.dataa(A_c_0),
	.datab(B_c_0),
	.datac(COUT_0)
);
defparam COUT_1.operation_mode="normal";
defparam COUT_1.output_mode="comb_only";
defparam COUT_1.lut_mask="7171";
defparam COUT_1.synch_mode="off";
defparam COUT_1.sum_lutc_input="datac";
// @2:15
  cyclone_lcell SUM_0 (
	.combout(SUM),
	.dataa(A_c_0),
	.datab(B_c_0),
	.datac(COUT_0)
);
defparam SUM_0.operation_mode="normal";
defparam SUM_0.output_mode="comb_only";
defparam SUM_0.lut_mask="6969";
defparam SUM_0.synch_mode="off";
defparam SUM_0.sum_lutc_input="datac";
endmodule /* Full_Adder_5 */

module Full_Adder_6 (
  B_c_0,
  A_c_0,
  SUM,
  COUT_0,
  COUT
);
input B_c_0 ;
input A_c_0 ;
output SUM ;
input COUT_0 ;
output COUT ;
wire B_c_0 ;
wire A_c_0 ;
wire SUM ;
wire COUT_0 ;
wire COUT ;
wire GND ;
wire VCC ;
  assign VCC = 1'b1;
  assign GND = 1'b0;
// @2:16
  cyclone_lcell COUT_1 (
	.combout(COUT),
	.dataa(A_c_0),
	.datab(B_c_0),
	.datac(COUT_0)
);
defparam COUT_1.operation_mode="normal";
defparam COUT_1.output_mode="comb_only";
defparam COUT_1.lut_mask="7171";
defparam COUT_1.synch_mode="off";
defparam COUT_1.sum_lutc_input="datac";
// @2:15
  cyclone_lcell SUM_0 (
	.combout(SUM),
	.dataa(A_c_0),
	.datab(B_c_0),
	.datac(COUT_0)
);
defparam SUM_0.operation_mode="normal";
defparam SUM_0.output_mode="comb_only";
defparam SUM_0.lut_mask="6969";
defparam SUM_0.synch_mode="off";
defparam SUM_0.sum_lutc_input="datac";
endmodule /* Full_Adder_6 */

module Full_Adder_7 (
  B_c_0,
  A_c_0,
  SUM,
  COUT_0,
  COUT
);
input B_c_0 ;
input A_c_0 ;
output SUM ;
input COUT_0 ;
output COUT ;
wire B_c_0 ;
wire A_c_0 ;
wire SUM ;
wire COUT_0 ;
wire COUT ;
wire GND ;
wire VCC ;
  assign VCC = 1'b1;
  assign GND = 1'b0;
// @2:16
  cyclone_lcell COUT_1 (
	.combout(COUT),
	.dataa(A_c_0),
	.datab(B_c_0),
	.datac(COUT_0)
);
defparam COUT_1.operation_mode="normal";
defparam COUT_1.output_mode="comb_only";
defparam COUT_1.lut_mask="7171";
defparam COUT_1.synch_mode="off";
defparam COUT_1.sum_lutc_input="datac";
// @2:15
  cyclone_lcell SUM_0 (
	.combout(SUM),
	.dataa(A_c_0),
	.datab(B_c_0),
	.datac(COUT_0)
);
defparam SUM_0.operation_mode="normal";
defparam SUM_0.output_mode="comb_only";
defparam SUM_0.lut_mask="6969";
defparam SUM_0.synch_mode="off";
defparam SUM_0.sum_lutc_input="datac";
endmodule /* Full_Adder_7 */

module AdderE (
  A,
  B,
  CIN,
  COUT,
  SUM
);
input [7:0] A ;
input [7:0] B ;
input CIN ;
output COUT /* synthesis syn_tristate = 1 */;
output [7:0] SUM /* synthesis syn_tristate = 1 */;
wire CIN ;
wire COUT ;
wire [7:0] B_c;
wire [7:0] A_c;
wire VCC ;
wire GND ;
wire CIN_c ;
wire Stages_7_OtherBits_FA_SUM ;
wire Stages_6_OtherBits_FA_SUM ;
wire Stages_5_OtherBits_FA_SUM ;
wire Stages_4_OtherBits_FA_SUM ;
wire Stages_3_OtherBits_FA_SUM ;
wire Stages_2_OtherBits_FA_SUM ;
wire Stages_1_OtherBits_FA_SUM ;
wire Stages_0_LowBit_FA_SUM ;
wire N_5_i ;
wire Stages_0_LowBit_FA_COUT ;
wire Stages_5_OtherBits_FA_COUT ;
wire Stages_6_OtherBits_FA_COUT ;
wire Stages_1_OtherBits_FA_COUT ;
wire Stages_4_OtherBits_FA_COUT ;
wire Stages_2_OtherBits_FA_COUT ;
wire Stages_3_OtherBits_FA_COUT ;
//@1:1
  assign VCC = 1'b1;
//@1:1
  assign GND = 1'b0;
// @3:5
  cyclone_io CIN_in (
	.padio(CIN),
	.combout(CIN_c),
	.oe(GND)
);
defparam CIN_in.operation_mode = "input";
// @3:4
  cyclone_io B_in_7_ (
	.padio(B[7]),
	.combout(B_c[7]),
	.oe(GND)
);
defparam B_in_7_.operation_mode = "input";
// @3:4
  cyclone_io B_in_6_ (
	.padio(B[6]),
	.combout(B_c[6]),
	.oe(GND)
);
defparam B_in_6_.operation_mode = "input";
// @3:4
  cyclone_io B_in_5_ (
	.padio(B[5]),
	.combout(B_c[5]),
	.oe(GND)
);
defparam B_in_5_.operation_mode = "input";
// @3:4
  cyclone_io B_in_4_ (
	.padio(B[4]),
	.combout(B_c[4]),
	.oe(GND)
);
defparam B_in_4_.operation_mode = "input";
// @3:4
  cyclone_io B_in_3_ (
	.padio(B[3]),
	.combout(B_c[3]),
	.oe(GND)
);
defparam B_in_3_.operation_mode = "input";
// @3:4
  cyclone_io B_in_2_ (
	.padio(B[2]),
	.combout(B_c[2]),
	.oe(GND)
);
defparam B_in_2_.operation_mode = "input";
// @3:4
  cyclone_io B_in_1_ (
	.padio(B[1]),
	.combout(B_c[1]),
	.oe(GND)
);
defparam B_in_1_.operation_mode = "input";
// @3:4
  cyclone_io B_in_0_ (
	.padio(B[0]),
	.combout(B_c[0]),
	.oe(GND)
);
defparam B_in_0_.operation_mode = "input";
// @3:4
  cyclone_io A_in_7_ (
	.padio(A[7]),
	.combout(A_c[7]),
	.oe(GND)
);
defparam A_in_7_.operation_mode = "input";
// @3:4
  cyclone_io A_in_6_ (
	.padio(A[6]),
	.combout(A_c[6]),
	.oe(GND)
);
defparam A_in_6_.operation_mode = "input";
// @3:4
  cyclone_io A_in_5_ (
	.padio(A[5]),
	.combout(A_c[5]),
	.oe(GND)
);
defparam A_in_5_.operation_mode = "input";
// @3:4
  cyclone_io A_in_4_ (
	.padio(A[4]),
	.combout(A_c[4]),
	.oe(GND)
);
defparam A_in_4_.operation_mode = "input";
// @3:4
  cyclone_io A_in_3_ (
	.padio(A[3]),
	.combout(A_c[3]),
	.oe(GND)
);
defparam A_in_3_.operation_mode = "input";
// @3:4
  cyclone_io A_in_2_ (
	.padio(A[2]),
	.combout(A_c[2]),
	.oe(GND)
);
defparam A_in_2_.operation_mode = "input";
// @3:4
  cyclone_io A_in_1_ (
	.padio(A[1]),
	.combout(A_c[1]),
	.oe(GND)
);
defparam A_in_1_.operation_mode = "input";
// @3:4
  cyclone_io A_in_0_ (
	.padio(A[0]),
	.combout(A_c[0]),
	.oe(GND)
);
defparam A_in_0_.operation_mode = "input";
// @3:7
  cyclone_io SUM_out_7_ (
	.padio(SUM[7]),
	.datain(Stages_7_OtherBits_FA_SUM),
	.oe(VCC)
);
defparam SUM_out_7_.operation_mode = "output";
// @3:7
  cyclone_io SUM_out_6_ (
	.padio(SUM[6]),
	.datain(Stages_6_OtherBits_FA_SUM),
	.oe(VCC)
);
defparam SUM_out_6_.operation_mode = "output";
// @3:7
  cyclone_io SUM_out_5_ (
	.padio(SUM[5]),
	.datain(Stages_5_OtherBits_FA_SUM),
	.oe(VCC)
);
defparam SUM_out_5_.operation_mode = "output";
// @3:7
  cyclone_io SUM_out_4_ (
	.padio(SUM[4]),
	.datain(Stages_4_OtherBits_FA_SUM),
	.oe(VCC)
);
defparam SUM_out_4_.operation_mode = "output";
// @3:7
  cyclone_io SUM_out_3_ (
	.padio(SUM[3]),
	.datain(Stages_3_OtherBits_FA_SUM),
	.oe(VCC)
);
defparam SUM_out_3_.operation_mode = "output";
// @3:7
  cyclone_io SUM_out_2_ (
	.padio(SUM[2]),
	.datain(Stages_2_OtherBits_FA_SUM),
	.oe(VCC)
);
defparam SUM_out_2_.operation_mode = "output";
// @3:7
  cyclone_io SUM_out_1_ (
	.padio(SUM[1]),
	.datain(Stages_1_OtherBits_FA_SUM),
	.oe(VCC)
);
defparam SUM_out_1_.operation_mode = "output";
// @3:7
  cyclone_io SUM_out_0_ (
	.padio(SUM[0]),
	.datain(Stages_0_LowBit_FA_SUM),
	.oe(VCC)
);
defparam SUM_out_0_.operation_mode = "output";
// @3:6
  cyclone_io COUT_out (
	.padio(COUT),
	.datain(N_5_i),
	.oe(VCC)
);
defparam COUT_out.operation_mode = "output";
// @3:23
  Full_Adder Stages_0_LowBit_FA (
	.B_c_0(B_c[0]),
	.A_c_0(A_c[0]),
	.SUM(Stages_0_LowBit_FA_SUM),
	.CIN_c(CIN_c),
	.COUT(Stages_0_LowBit_FA_COUT)
);
// @3:26
  Full_Adder_1 Stages_6_OtherBits_FA (
	.B_c_0(B_c[6]),
	.A_c_0(A_c[6]),
	.SUM(Stages_6_OtherBits_FA_SUM),
	.COUT_0(Stages_5_OtherBits_FA_COUT),
	.COUT(Stages_6_OtherBits_FA_COUT)
);
// @3:26
  Full_Adder_2 Stages_1_OtherBits_FA (
	.B_c_0(B_c[1]),
	.A_c_0(A_c[1]),
	.SUM(Stages_1_OtherBits_FA_SUM),
	.COUT_0(Stages_0_LowBit_FA_COUT),
	.COUT(Stages_1_OtherBits_FA_COUT)
);
// @3:26
  Full_Adder_3 Stages_7_OtherBits_FA (
	.B_c_0(B_c[7]),
	.A_c_0(A_c[7]),
	.SUM(Stages_7_OtherBits_FA_SUM),
	.COUT(Stages_6_OtherBits_FA_COUT),
	.N_5_i(N_5_i)
);
// @3:26
  Full_Adder_4 Stages_5_OtherBits_FA (
	.B_c_0(B_c[5]),
	.A_c_0(A_c[5]),
	.SUM(Stages_5_OtherBits_FA_SUM),
	.COUT_0(Stages_4_OtherBits_FA_COUT),
	.COUT(Stages_5_OtherBits_FA_COUT)
);
// @3:26
  Full_Adder_5 Stages_2_OtherBits_FA (
	.B_c_0(B_c[2]),
	.A_c_0(A_c[2]),
	.SUM(Stages_2_OtherBits_FA_SUM),
	.COUT_0(Stages_1_OtherBits_FA_COUT),
	.COUT(Stages_2_OtherBits_FA_COUT)
);
// @3:26
  Full_Adder_6 Stages_3_OtherBits_FA (
	.B_c_0(B_c[3]),
	.A_c_0(A_c[3]),
	.SUM(Stages_3_OtherBits_FA_SUM),
	.COUT_0(Stages_2_OtherBits_FA_COUT),
	.COUT(Stages_3_OtherBits_FA_COUT)
);
// @3:26
  Full_Adder_7 Stages_4_OtherBits_FA (
	.B_c_0(B_c[4]),
	.A_c_0(A_c[4]),
	.SUM(Stages_4_OtherBits_FA_SUM),
	.COUT_0(Stages_3_OtherBits_FA_COUT),
	.COUT(Stages_4_OtherBits_FA_COUT)
);
endmodule /* AdderE */