ddfsdemo.map.qmsg

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jun 11 14:15:28 2006 " "Info: Processing started: Sun Jun 11 14:15:28 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off DDFSDemo -c DDFSDemo " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DDFSDemo -c DDFSDemo" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DDFSDemo.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file DDFSDemo.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 DDFSDemo " "Info: Found entity 1: DDFSDemo" {  } { { "DDFSDemo.bdf" "" { Schematic "D:/QProj/DDFSDemo/DDFSDemo.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DDFSCore.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file DDFSCore.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 DDFSCore-behavioural " "Info: Found design unit 1: DDFSCore-behavioural" {  } { { "DDFSCore.vhd" "" { Text "D:/QProj/DDFSDemo/DDFSCore.vhd" 70 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 DDFSCore " "Info: Found entity 1: DDFSCore" {  } { { "DDFSCore.vhd" "" { Text "D:/QProj/DDFSDemo/DDFSCore.vhd" 36 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "DDFSDemo " "Info: Elaborating entity \"DDFSDemo\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DDFSCore DDFSCore:inst3 " "Info: Elaborating entity \"DDFSCore\" for hierarchy \"DDFSCore:inst3\"" {  } { { "DDFSDemo.bdf" "inst3" { Schematic "D:/QProj/DDFSDemo/DDFSDemo.bdf" { { -688 48 456 -528 "inst3" "" } } } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "clk_G_SystemClock DDFSCore.vhd(76) " "Info: (10035) Verilog HDL or VHDL information at DDFSCore.vhd(76): object \"clk_G_SystemClock\" declared but not used" {  } { { "DDFSCore.vhd" "" { Text "D:/QProj/DDFSDemo/DDFSCore.vhd" 76 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 425 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram DDFSCore:inst3\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"DDFSCore:inst3\|altsyncram:altsyncram_component\"" {  } { { "DDFSCore.vhd" "altsyncram_component" { Text "D:/QProj/DDFSDemo/DDFSCore.vhd" 136 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_tme1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_tme1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_tme1 " "Info: Found entity 1: altsyncram_tme1" {  } { { "db/altsyncram_tme1.tdf" "" { Text "D:/QProj/DDFSDemo/db/altsyncram_tme1.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_tme1 DDFSCore:inst3\|altsyncram:altsyncram_component\|altsyncram_tme1:auto_generated " "Info: Elaborating entity \"altsyncram_tme1\" for hierarchy \"DDFSCore:inst3\|altsyncram:altsyncram_component\|altsyncram_tme1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "PLL.vhd 2 1 " "Info: Using design file PLL.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 PLL-SYN " "Info: Found design unit 1: PLL-SYN" {  } { { "PLL.vhd" "" { Text "D:/QProj/DDFSDemo/PLL.vhd" 48 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 PLL " "Info: Found entity 1: PLL" {  } { { "PLL.vhd" "" { Text "D:/QProj/DDFSDemo/PLL.vhd" 39 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "PLL PLL:inst " "Info: Elaborating entity \"PLL\" for hierarchy \"PLL:inst\"" {  } { { "DDFSDemo.bdf" "inst" { Schematic "D:/QProj/DDFSDemo/DDFSDemo.bdf" { { -720 -296 -56 -560 "inst" "" } } } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/altpll.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/altpll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll " "Info: Found entity 1: altpll" {  } { { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 363 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll PLL:inst\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"PLL:inst\|altpll:altpll_component\"" {  } { { "PLL.vhd" "altpll_component" { Text "D:/QProj/DDFSDemo/PLL.vhd" 86 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "131 " "Info: Implemented 131 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "50 " "Info: Implemented 50 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "64 " "Info: Implemented 64 logic cells" {  } {  } 0} { "Info" "ISCL_SCL_TM_RAMS" "8 " "Info: Implemented 8 RAM segments" {  } {  } 0} { "Info" "ISCL_SCL_TM_PLLS" "1 " "Info: Implemented 1 ClockLock PLLs" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Jun 11 14:15:33 2006 " "Info: Processing ended: Sun Jun 11 14:15:33 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0}  } {  } 0}