mux_vab.tdf

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone" LPM_SIZE=2 LPM_WIDTH=8 LPM_WIDTHS=1 data result sel
--VERSION_BEGIN 5.0 cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:04:13:17:26:48:SJ  VERSION_END


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--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.



--synthesis_resources = lut 8 
SUBDESIGN mux_vab
( 
	data[15..0]	:	input;
	result[7..0]	:	output;
	sel[0..0]	:	input;
) 
VARIABLE 
	result_node[7..0]	: WIRE;
	sel_node[0..0]	: WIRE;
	w_data153w[1..0]	: WIRE;
	w_data167w[1..0]	: WIRE;
	w_data179w[1..0]	: WIRE;
	w_data191w[1..0]	: WIRE;
	w_data203w[1..0]	: WIRE;
	w_data215w[1..0]	: WIRE;
	w_data227w[1..0]	: WIRE;
	w_data239w[1..0]	: WIRE;
	w_result154w	: WIRE;
	w_result160w	: WIRE;
	w_result168w	: WIRE;
	w_result174w	: WIRE;
	w_result180w	: WIRE;
	w_result186w	: WIRE;
	w_result192w	: WIRE;
	w_result198w	: WIRE;
	w_result204w	: WIRE;
	w_result210w	: WIRE;
	w_result216w	: WIRE;
	w_result222w	: WIRE;
	w_result228w	: WIRE;
	w_result234w	: WIRE;
	w_result240w	: WIRE;
	w_result246w	: WIRE;

BEGIN 
	result[] = result_node[];
	result_node[] = ( w_result240w, w_result228w, w_result216w, w_result204w, w_result192w, w_result180w, w_result168w, w_result154w);
	sel_node[] = ( sel[0..0]);
	w_data153w[] = ( data[8..8], data[0..0]);
	w_data167w[] = ( data[9..9], data[1..1]);
	w_data179w[] = ( data[10..10], data[2..2]);
	w_data191w[] = ( data[11..11], data[3..3]);
	w_data203w[] = ( data[12..12], data[4..4]);
	w_data215w[] = ( data[13..13], data[5..5]);
	w_data227w[] = ( data[14..14], data[6..6]);
	w_data239w[] = ( data[15..15], data[7..7]);
	w_result154w = w_result160w;
	w_result160w = ((sel_node[] & w_data153w[1..1]) # ((! sel_node[]) & w_data153w[0..0]));
	w_result168w = w_result174w;
	w_result174w = ((sel_node[] & w_data167w[1..1]) # ((! sel_node[]) & w_data167w[0..0]));
	w_result180w = w_result186w;
	w_result186w = ((sel_node[] & w_data179w[1..1]) # ((! sel_node[]) & w_data179w[0..0]));
	w_result192w = w_result198w;
	w_result198w = ((sel_node[] & w_data191w[1..1]) # ((! sel_node[]) & w_data191w[0..0]));
	w_result204w = w_result210w;
	w_result210w = ((sel_node[] & w_data203w[1..1]) # ((! sel_node[]) & w_data203w[0..0]));
	w_result216w = w_result222w;
	w_result222w = ((sel_node[] & w_data215w[1..1]) # ((! sel_node[]) & w_data215w[0..0]));
	w_result228w = w_result234w;
	w_result234w = ((sel_node[] & w_data227w[1..1]) # ((! sel_node[]) & w_data227w[0..0]));
	w_result240w = w_result246w;
	w_result246w = ((sel_node[] & w_data239w[1..1]) # ((! sel_node[]) & w_data239w[0..0]));
END;
--VALID FILE