📄 ctr.fit.rpt
字号:
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 2 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 0 ;
; 16 ; 1 ;
+----------------------------------------+-----------------------------+
+---------------------------------------------------------+
; Parallel Expander ;
+--------------------------+------------------------------+
; Parallel Expander Length ; Number of Parallel Expanders ;
+--------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 2 ;
+--------------------------+------------------------------+
+-------------------------------------------------------------------------------+
; Shareable Expander ;
+-------------------------------------------------+-----------------------------+
; Number of shareable expanders (Average = 1.00) ; Number of LABs (Total = 1) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 3 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 1 ;
+-------------------------------------------------+-----------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection ;
+-----+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; LAB ; Logic Cell ; Input ; Output ;
+-----+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; A ; LC1 ; ; pa2 ;
; B ; LC17 ; ; pa7 ;
; B ; LC19 ; busy ; fifowr ;
; B ; LC27 ; clk, empty, Uflag[1] ; fiford~reg0 ;
; B ; LC25 ; ; pa4 ;
; B ; LC26 ; clk, pa_in[1], pa_in[0], pa3, counter64[0], counter64[1], reset ; counter64[7], counter16[0], counter16[3], counter16[4], counter16[5], counter64[1], counter16[1], counter64[2], counter16[2], counter64[3], counter64[4], counter64[5], counter64[6], addr~3325, addr[0]~reg0, r_c~reg0, addr[1]~reg0, addr[3]~reg0, addr[2]~reg0, addr[1]~3358, addr[1]~3361, addr~3367, addr~3371 ;
; B ; LC30 ; clk, pa_in[1], pa_in[0], pa3, counter64[0], reset ; counter64[0], counter64[7], counter16[0], counter16[3], counter16[4], counter16[5], counter64[1], counter16[1], counter64[2], counter16[2], counter64[3], counter64[4], counter64[5], counter64[6], addr~3325, addr[0]~reg0, r_c~reg0, addr[1]~reg0, addr[3]~reg0, addr[2]~reg0, addr[1]~3358, addr[1]~3361, addr~3367, addr~3371 ;
; B ; LC20 ; clk, q[0], empty, Uflag[1] ; fiford, fiford~14 ;
; B ; LC18 ; clk, pa_in[1], pa_in[0], pa3, counter64[2], counter64[0], counter64[1], reset ; counter64[7], counter16[0], counter16[3], counter16[4], counter16[5], counter16[1], counter64[2], counter16[2], counter64[3], counter64[4], counter64[5], counter64[6], addr~3325, addr[0]~reg0, r_c~reg0, addr[1]~reg0, addr[3]~reg0, addr[2]~reg0, addr[1]~3358, addr[1]~3361, addr~3367, addr~3371 ;
; B ; LC24 ; ; pa5 ;
; B ; LC21 ; ; pa6 ;
; C ; LC33 ; clk, counter64[6], counter64[5], counter64[4], counter64[3], counter64[2], counter64[0], counter64[1], counter64[7], pa_in[1], pa_in[0], pa3, reset ; counter64[7], counter16[0], counter16[3], counter16[4], counter16[5], counter16[1], counter16[2], addr~3325, addr[0]~reg0, r_c~reg0, addr[1]~reg0, addr[3]~reg0, addr[2]~reg0, addr[1]~3358, addr[1]~3361, addr~3367, addr~3371 ;
; C ; LC34 ; clk, pa_in[1], pa_in[0], pa3, reset, counter64[7], counter64[6], counter64[5], counter64[4], counter64[3], counter64[0], counter64[2], counter64[1], counter16[0] ; counter16[0], counter16[3], counter16[4], counter16[5], counter16[1], counter16[2], addr[0]~reg0, addr[1]~3335, addr[1]~reg0, addr[3]~reg0, addr[1]~3358, addr[1]~3361, addr~3367, addr~3371, addr[2]~reg0 ;
; C ; LC39 ; clk, counter16[2], counter16[0], counter16[1], counter64[7], counter64[6], counter64[5], counter64[4], counter64[3], counter64[0], counter64[2], counter64[1], pa_in[1], pa_in[0], pa3, reset, counter16[3] ; counter16[3], counter16[4], counter16[5], addr~3326, addr[0]~reg0, addr[1]~3337, addr[1]~reg0, addr[2]~reg0, addr[1]~3358, addr[1]~3361, addr~3367, addr~3371, addr[3]~reg0 ;
; C ; LC41 ; clk, counter16[5], counter16[3], counter16[2], counter16[0], counter16[1], counter64[7], counter64[6], counter64[5], counter64[4], counter64[3], counter64[0], counter64[2], counter64[1], pa_in[1], pa_in[0], pa3, reset, counter16[4] ; counter16[4], counter16[5], addr~3325, addr[0]~reg0, addr[1]~reg0, addr[3]~reg0, addr[2]~reg0, addr[1]~3358, addr[1]~3361, addr~3367, addr~3371 ;
; C ; LC38 ; clk, counter16[4], counter16[3], counter16[2], counter16[0], counter16[1], counter64[7], counter64[6], counter64[5], counter64[4], counter64[3], counter64[0], counter64[2], counter64[1], pa_in[1], pa_in[0], pa3, reset, counter16[5] ; counter16[4], counter16[5], addr~3325, addr[0]~reg0, addr[1]~reg0, addr[3]~reg0, addr[2]~reg0, addr[1]~3358, addr[1]~3361, addr~3367, addr~3371 ;
; C ; LC43 ; clk, pa_in[1], pa_in[0], pa3, counter16[0], reset, counter64[7], counter64[6], counter64[5], counter64[4], counter64[3], counter64[0], counter64[2], counter64[1], counter16[1] ; counter16[3], counter16[4], counter16[5], counter16[1], counter16[2], addr[0]~reg0, addr[1]~3337, addr[1]~reg0, addr[3]~reg0, addr[2]~reg0, addr[1]~3358, addr[1]~3361, addr~3367, addr~3371 ;
; C ; LC48 ; clk, counter16[0], counter16[1], counter64[7], counter64[6], counter64[5], counter64[4], counter64[3], counter64[0], counter64[2], counter64[1], pa_in[1], pa_in[0], pa3, reset, counter16[2] ; counter16[3], counter16[4], counter16[5], counter16[2], addr~3326, addr[0]~reg0, addr[1]~3335, addr[1]~reg0, addr[3]~reg0, addr[2]~reg0, addr[1]~3358, addr[1]~3361, addr~3367, addr~3371 ;
; C ; LC36 ; pa_in[1], pa_in[0], pa3 ; rstfifo ;
; C ; LC35 ; clk, pa_in[1], pa_in[0], pa3, counter64[3], counter64[2], counter64[0], counter64[1], counter64[4], reset ; counter64[7], counter16[0], counter16[3], counter16[4], counter16[5], counter16[1], counter16[2], counter64[4], counter64[5], counter64[6], addr~3325, addr[0]~reg0, r_c~reg0, addr[1]~reg0, addr[3]~reg0, addr[2]~reg0, addr[1]~3358, addr[1]~3361, addr~3367, addr~3371 ;
; C ; LC47 ; clk, pa_in[1], pa_in[0], pa3, counter64[4], counter64[3], counter64[2], counter64[0], counter64[1], counter64[5], reset ; counter64[7], counter16[0], counter16[3], counter16[4], counter16[5], counter16[1], counter16[2], counter64[5], counter64[6], addr~3325, addr[0]~reg0, r_c~reg0, addr[1]~reg0, addr[3]~reg0, addr[2]~reg0, addr[1]~3358, addr[1]~3361, addr~3367, addr~3371 ;
; C ; LC42 ; clk, pa_in[1], pa_in[0], pa3, counter64[5], counter64[4], counter64[3], counter64[2], counter64[0], counter64[1], counter64[6], reset ; counter64[7], counter16[0], counter16[3], counter16[4], counter16[5], counter16[1], counter16[2], counter64[6], addr~3325, addr[0]~reg0, r_c~reg0, addr[1]~reg0, addr[3]~reg0, addr[2]~reg0, addr[1]~3358, addr[1]~3361, addr~3367, addr~3371 ;
; C ; LC46 ; clk, addr[1]~3361, counter16[4], counter16[5], counter16[1], counter16[2], counter16[0], counter64[7], counter64[6], counter64[5], counter64[4], counter64[3], counter64[0], counter64[2], counter64[1], addr[3]~reg0, pa_in[1], pa_in[0], pa3, reset, counter16[3] ; addr[3]~reg0, addr[3], addr[1]~3358, addr[1]~3361 ;
; C ; LC44 ; counter16[3], counter16[4], counter16[5], counter16[1], counter16[0], counter64[7], counter64[6], counter64[5], counter64[4], counter64[3], counter64[0], counter64[2], counter64[1], addr[3]~reg0, counter16[2] ; addr[1]~3361 ;
; C ; LC45 ; addr[1]~3358, counter16[3], counter16[4], counter16[5], counter16[1], counter16[2], counter64[7], counter64[6], counter64[5], counter64[4], counter64[3], counter64[0], counter64[2], counter64[1], pa_in[1], pa_in[0], pa3, addr[3]~reg0, counter16[0] ; addr[3]~reg0 ;
; C ; LC37 ; clk, pa_in[1], pa_in[0], pa3, reset ; led1 ;
; C ; LC40 ; pa_in[1], pa_in[0], pa3 ; led2 ;
; D ; LC53 ; clk, pa_in[1], pa_in[0], pa3, r_c~reg0, counter64[7], counter64[6], counter64[5], counter64[4], counter64[0], counter64[2], counter64[1], counter64[3], reset ; r_c~reg0, r_c ;
; D ; LC51 ; clk, addr~3325, pa_in[1], pa_in[0], pa3, addr[1]~reg0, addr[1]~3335, counter16[3], counter16[1], counter16[4], counter16[5], counter64[7], counter64[6], counter64[5], counter64[4], counter64[3], counter64[0], counter64[2], counter64[1], addr~3326, counter16[0], addr[1]~3337, counter16[2], reset ; addr[1]~reg0, addr[1] ;
; D ; LC55 ; counter16[3], counter16[2], counter64[7], counter64[6], counter64[5], counter64[4], counter64[3], counter64[0], counter64[2], counter64[1], counter16[4], counter16[5], addr[2]~reg0, counter16[0], counter16[1] ; addr~3371 ;
; D ; LC56 ; addr~3367, counter16[0], counter16[1], counter16[2], counter64[7], counter64[6], counter64[5], counter64[4], counter64[3], counter64[0], counter64[2], counter64[1], counter16[4], counter16[5], pa_in[1], pa_in[0], pa3, addr[2]~reg0, counter16[3] ; addr[2]~reg0 ;
; D ; LC64 ; ; slrd ;
; D ; LC62 ; fiford~reg0 ; slwr ;
; D ; LC52 ; pa_in[1], pa_in[0], pa3 ; ctr ;
; D ; LC49 ; clk, counter64[7], pa_in[1], pa_in[0], pa3, counter64[6], counter64[5], counter64[4], counter64[3], counter64[0], counter64[2], counter64[1], counter16[0], counter16[3], counter16[1], counter16[2], counter16[4], counter16[5], addr~3325, addr[0]~reg0, addr~3326, reset ; addr[0]~reg0, addr[0] ;
; D ; LC57 ; clk, addr~3371, counter16[3], counter16[1], counter16[2], counter64[7], counter64[6], counter64[5], counter64[4], counter64[3], counter64[0], counter64[2], counter64[1], counter16[4], counter16[5], addr[2]~reg0, pa_in[1], pa_in[0], pa3, reset, counter16[0] ; addr[2]~reg0, addr[2], addr~3367, addr~3371 ;
; D ; LC50 ; clk, pa_in[1], pa_in[0], pa3, counter64[3], counter64[2], counter64[0], counter64[1], reset ; counter64[7], counter16[0], counter16[3], counter16[4], counter16[5], counter16[1], counter16[2], counter64[3], counter64[4], counter64[5], counter64[6], addr~3325, addr[0]~reg0, r_c~reg0, addr[1]~reg0, addr[3]~reg0, addr[2]~reg0, addr[1]~3358, addr[1]~3361, addr~3367, addr~3371 ;
+-----+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+-------------------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+--------------------------+
; Option ; Setting ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Passive Serial ;
; Reserve all unused pins ; As output driving ground ;
; Security bit ; Off ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+--------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Web Edition
Info: Processing started: Fri Dec 01 14:22:47 2006
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off ctr -c ctr
Info: Selected device EPM7064AETC44-4 for design "ctr"
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Fri Dec 01 14:22:48 2006
Info: Elapsed time: 00:00:01
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -