inv_mixcolumns.v

使用Verilog HDL 實現AES硬體加解密

module Inv_MixColumns (data_in, data_out);

parameter	AES_length = 128;
input	[AES_length-1:0] data_in;
output	[AES_length-1:0] data_out;
				
wire	[7:0]	in00,in01,in02,in03,
				in10,in11,in12,in13,
				in20,in21,in22,in23,
				in30,in31,in32,in33;
				
wire	[7:0]	out00,out01,out02,out03,
				out10,out11,out12,out13,
				out20,out21,out22,out23,
				out30,out31,out32,out33;	

assign	{	in33,in23,in13,in03,
			in32,in22,in12,in02,
			in31,in21,in11,in01,
			in30,in20,in10,in00	} = data_in;
			
assign	data_out = {	out33,out23,out13,out03,
						out32,out22,out12,out02,
						out31,out21,out11,out01,
						out30,out20,out10,out00	};

Inv_Columns_Block	u0(	.i_0c(in00), .i_1c(in10), .i_2c(in20), .i_3c(in30),
						.o_0c(out00), .o_1c(out10), .o_2c(out20), .o_3c(out30) );
Inv_Columns_Block	u1(	.i_0c(in01), .i_1c(in11), .i_2c(in21), .i_3c(in31),
						.o_0c(out01), .o_1c(out11), .o_2c(out21), .o_3c(out31) );
Inv_Columns_Block	u2(	.i_0c(in02), .i_1c(in12), .i_2c(in22), .i_3c(in32),
						.o_0c(out02), .o_1c(out12), .o_2c(out22), .o_3c(out32) );
Inv_Columns_Block	u3(	.i_0c(in03), .i_1c(in13), .i_2c(in23), .i_3c(in33),
						.o_0c(out03), .o_1c(out13), .o_2c(out23), .o_3c(out33) );
						
endmodule				
						
module Inv_Columns_Block (	i_0c, i_1c, i_2c, i_3c,
							o_0c, o_1c, o_2c, o_3c );
							
input	[7:0] i_0c, i_1c, i_2c, i_3c;
output	[7:0] o_0c, o_1c, o_2c, o_3c;

wire	[7:0] x3_0, x2_0, x2_1;
wire	[7:0] x1_0, x1_1, x1_2, x1_3;

//xtime (08)							
xtime3	u01(.xin(i_0c^i_1c^i_2c^i_3c), .xout(x3_0));
//xtime (04)
xtime2	u02(.xin(i_0c^i_2c), .xout(x2_0));
xtime2	u03(.xin(i_1c^i_3c), .xout(x2_1));
//xtime (02)
xtime	u0(.xin(i_0c^i_1c),.xout(x1_0));
xtime	u1(.xin(i_1c^i_2c),.xout(x1_1));
xtime	u2(.xin(i_2c^i_3c),.xout(x1_2));
xtime	u3(.xin(i_3c^i_0c),.xout(x1_3));

assign	o_0c = x3_0 ^ x2_0 ^ x1_0 ^ i_1c ^ i_2c ^ i_3c;
assign	o_1c = x3_0 ^ x2_1 ^ x1_1 ^ i_0c ^ i_2c ^ i_3c;
assign	o_2c = x3_0 ^ x2_0 ^ x1_2 ^ i_0c ^ i_1c ^ i_3c;
assign	o_3c = x3_0 ^ x2_1 ^ x1_3 ^ i_0c ^ i_1c ^ i_2c;
						
endmodule

module xtime3(xin, xout);		//xtime(08)
input	[7:0] xin;
output	[7:0] xout;

wire	[7:0] x1_out, x2_out;

xtime	u1(.xin(xin), .xout(x1_out));
xtime	u2(.xin(x1_out), .xout(x2_out));
xtime	u3(.xin(x2_out), .xout(xout));

endmodule

module xtime2(xin, xout);		//xtime(04)
input	[7:0] xin;
output	[7:0] xout;

wire	[7:0] x1_out;

xtime	u1(.xin(xin), .xout(x1_out));
xtime	u2(.xin(x1_out), .xout(xout));

endmodule

module xtime (xin, xout);		//xtime(02)
input	[7:0] xin;
output	[7:0] xout;

	assign	xout = xin[7]?((xin<<1)^8'H1B):(xin<<1);
	
endmodule