inv_subbytes.v

使用Verilog HDL 實現AES硬體加解密

module Inv_SubBytes(clk, clk_enable, data_in, data_out);

parameter AES_length = 128;

input	clk, clk_enable;
input	[AES_length-1:0] data_in;
output	[AES_length-1:0] data_out;


wire	[7:0] 	in15,in14,in13,in12,
				in11,in10,in09,in08,
				in07,in06,in05,in04,
				in03,in02,in01,in00;


wire	[7:0] 	out15,out14,out13,out12,
				out11,out10,out09,out08,
				out07,out06,out05,out04,
				out03,out02,out01,out00;
								
							
assign	{	in15,in14,in13,in12,
			in11,in10,in09,in08,
			in07,in06,in05,in04,
			in03,in02,in01,in00	} = data_in;

assign	data_out = {	out15,out14,out13,out12,
						out11,out10,out09,out08,
						out07,out06,out05,out04,
						out03,out02,out01,out00 };
						
Inv_S_BOX_2PORT	u01(.clock(clk), .enable(clk_enable),
					.address_a(in00), .address_b(in01),
					.q_a(out00), .q_b(out01));

Inv_S_BOX_2PORT	u02(.clock(clk), .enable(clk_enable),
					.address_a(in02), .address_b(in03),
					.q_a(out02), .q_b(out03));
				
Inv_S_BOX_2PORT	u03(.clock(clk), .enable(clk_enable),
					.address_a(in04), .address_b(in05),
					.q_a(out04), .q_b(out05));
				
Inv_S_BOX_2PORT	u04(.clock(clk), .enable(clk_enable),
					.address_a(in06), .address_b(in07),
					.q_a(out06), .q_b(out07));

Inv_S_BOX_2PORT	u05(.clock(clk), .enable(clk_enable),
					.address_a(in08), .address_b(in09),
					.q_a(out08), .q_b(out09));

Inv_S_BOX_2PORT	u06(.clock(clk), .enable(clk_enable),
					.address_a(in10), .address_b(in11),
					.q_a(out10), .q_b(out11));
				
Inv_S_BOX_2PORT	u07(.clock(clk), .enable(clk_enable),
					.address_a(in12), .address_b(in13),
					.q_a(out12), .q_b(out13));
				
Inv_S_BOX_2PORT	u08(.clock(clk), .enable(clk_enable),
					.address_a(in14), .address_b(in15),
					.q_a(out14), .q_b(out15));
											
endmodule