decryption.v

来自「使用Verilog HDL 實現AES硬體加解密」· Verilog 代码 · 共 82 行

module decryption (	clk,
					sel,
					round,
					clken_sb,
					data_in,
					key_in,
					data_out,
					final_out
				  );

parameter AES_length = 128;
parameter AES_Round = 10;

input	clk, sel, clken_sb;
input	[3:0] round;
input	[AES_length-1:0] data_in;
input	[AES_length-1:0] key_in;

output	final_out;
output	[AES_length-1:0] data_out;

reg		final_out;
reg		[AES_length-1:0] data_out;

wire	[AES_length-1:0] 	Sel_1, Sel_2, Sel_out,
							Inv_ShiftRow_out, Inv_SubBytes_out, u2_out;

wire	clk_not;

assign	clk_not = ~clk;				
assign	Sel_out = sel?Sel_2:Sel_1;

always @(posedge clk)
begin
	if(!sel)
		final_out = 0;
		
	else
	begin
		if (round == AES_Round)
		begin
			data_out = u2_out;
			final_out = 1;
		end
	end

end

/*
always @(posedge clk)
begin
	if(!sel)
	begin
		i = 0;
		final_out = 0;
	end
	
	else
	begin
		if (i <= AES_Round)
			i = i + 1;
		
		if (i == AES_Round)
		begin
			data_out = u2_out;
			final_out = 1;
		end
		
		else
			final_out = 0;
	end
end
*/

AddRoundKey	u1(.data_in(data_in), .data_out(Sel_1), .key_in(key_in));
AddRoundKey u2(.data_in(Inv_SubBytes_out), .data_out(u2_out), .key_in(key_in));
Inv_ShiftRow u3(.data_in(Sel_out), .data_out(Inv_ShiftRow_out));
Inv_SubBytes u4(.clk(clk_not), .clk_enable(clken_sb), .data_in(Inv_ShiftRow_out), .data_out(Inv_SubBytes_out));
Inv_MixColumns u5(.data_in(u2_out), .data_out(Sel_2));

endmodule