keyexpansion.v

使用Verilog HDL 實現AES硬體加解密

module KeyExpansion (clk, reset, Key, read,
					 RoundKey_addr,
					 RoundKey_data,
					 test_temp1,
					 test_rom_data,
					 test_RotSub_out);

parameter AES_length = 128;

input	clk, reset;
input	[AES_length-1:0] Key;

output	read;
output	[3:0] RoundKey_addr;
output	[AES_length-1:0] RoundKey_data;

//test
output	[31:0] test_rom_data, test_RotSub_out;
output	[127:0] test_temp1;

assign	test_rom_data = rom_data;
assign	test_RotSub_out = RotSub_out;
assign	test_temp1 = temp1;
//

reg		read;
reg		state;
reg		[3:0] RoundKey_addr, i;
reg		[AES_length-1:0] RoundKey_data, temp;

wire	[31:0] 	rom_addr, rom_data, R_S, RotSub_in, RotSub_out,
				w0, w1, w2, w3;
wire	[AES_length-1:0] temp1, x0;

parameter	S0 = 1'b0, S1 = 1'b1;
parameter	Round = 11;

Rcon 		u1(.address(rom_addr), .clock(clk), .q(rom_data));
RotWord 	u2(.data_in(RotSub_in), .data_out(R_S));
SubWord 	u3(.clk(clk), .reset(reset), .data_in(R_S), .data_out(RotSub_out));
XorOperate 	u4(.clk(clk), .reset(reset), .Key(Key), .Rcon_in(rom_data), .SR_in(RotSub_out),
				.data_in(temp), .data_out(temp1));

assign	rom_addr = i;
assign	RotSub_in = w3;
assign	{w3, w2, w1, w0} = temp;

always @(posedge clk or negedge reset)	begin
			
if(!reset)	begin
	read = 1'b0;
	state = S0;
	i = 0;
end
				
else	begin
	case(state)
		S0:		
			begin
				if (i==Round)
					state = S1;
				else
				begin
					temp = temp1;
					RoundKey_data = temp;
					RoundKey_addr = i;
					i = i+1;					
					state = S0;
				end
			end
		S1:	read = 1'b1;
		
		default:	state = 1'bx;
	endcase
end

end

endmodule

module XorOperate (clk, reset,Key, Rcon_in, SR_in, data_in, data_out);

input	clk, reset;
input	[31:0] Rcon_in, SR_in;
input	[127:0] data_in,Key;
output	[127:0] data_out;

reg		[127:0] data_out;

wire	[31:0]	w0, w1, w2, w3,
				z0, z1, z2, z3;

assign	{w3, w2, w1, w0} = data_in;
//assign	data_out = {z3, z2, z1, z0};

assign	z0 = w0 ^ SR_in ^ Rcon_in;
assign	z1 = w1 ^ z0;
assign	z2 = w2 ^ z1;
assign	z3 = w3 ^ z2;

always @(posedge clk or negedge reset)
begin
	if (!reset)
		data_out = Key;
	else
		data_out = {z3, z2, z1, z0};
end
		
endmodule

module SubWord (clk, reset, data_in, data_out);

input	clk, reset;
input	[31:0] data_in;
output	[31:0] data_out;

//reg		[31:0] data_out;

wire	[7:0] 	i0, i1, i2, i3,
				o0, o1, o2, o3;

assign	{i3,i2,i1,i0} = data_in;
assign	data_out = {o3,o2,o1,o0};

S_BOX u01(.address(i0),	.clock(clk), .q(o0));
S_BOX u02(.address(i1), .clock(clk), .q(o1));
S_BOX u03(.address(i2), .clock(clk), .q(o2));
S_BOX u04(.address(i3), .clock(clk), .q(o3));	

/*
always @(posedge clk or negedge reset)
begin
	if(!reset)
		data_out = 0;
	else
		data_out = {o3,o2,o1,o0};
end	*/
endmodule

module RotWord (data_in, data_out);

input	[31:0] data_in;
output	[31:0] data_out;

wire	[7:0] a0, a1, a2, a3;

assign	{a3,a2,a1,a0} = data_in;
assign	data_out = {a0,a3,a2,a1};

endmodule