mixcolumn.v

使用Verilog HDL 實現AES硬體加解密

module MixColumn(data_in, data_out);

parameter	AES_length = 128;
input	[AES_length-1:0] data_in;
output	[AES_length-1:0] data_out;

wire	[7:0]	x00,x01,x02,x03,
				x10,x11,x12,x13,
				x20,x21,x22,x23,
				x30,x31,x32,x33;
				
wire	[7:0]	in00,in01,in02,in03,
				in10,in11,in12,in13,
				in20,in21,in22,in23,
				in30,in31,in32,in33;
				
wire	[7:0]	out00,out01,out02,out03,
				out10,out11,out12,out13,
				out20,out21,out22,out23,
				out30,out31,out32,out33;	

assign	{	in33,in23,in13,in03,
			in32,in22,in12,in02,
			in31,in21,in11,in01,
			in30,in20,in10,in00	} = data_in;
			
assign	data_out = {	out33,out23,out13,out03,
						out32,out22,out12,out02,
						out31,out21,out11,out01,
						out30,out20,out10,out00	};
						
xtime	u00(.xin(in00^in10),.xout(x00));
xtime	u10(.xin(in10^in20),.xout(x10));
xtime	u20(.xin(in20^in30),.xout(x20));
xtime	u30(.xin(in30^in00),.xout(x30));

xtime	u01(.xin(in01^in11),.xout(x01));
xtime	u11(.xin(in11^in21),.xout(x11));
xtime	u21(.xin(in21^in31),.xout(x21));
xtime	u31(.xin(in31^in01),.xout(x31));

xtime	u02(.xin(in02^in12),.xout(x02));
xtime	u12(.xin(in12^in22),.xout(x12));
xtime	u22(.xin(in22^in32),.xout(x22));
xtime	u32(.xin(in32^in02),.xout(x32));

xtime	u03(.xin(in03^in13),.xout(x03));
xtime	u13(.xin(in13^in23),.xout(x13));
xtime	u23(.xin(in23^in33),.xout(x23));
xtime	u33(.xin(in33^in03),.xout(x33));

assign	out00 = x00^in20^in30^in10;
assign	out10 = x10^in00^in30^in20;
assign	out20 = x20^in00^in10^in30;
assign	out30 = x30^in10^in20^in00;
assign	out01 = x01^in21^in31^in11;
assign	out11 = x11^in01^in31^in21;
assign	out21 = x21^in01^in11^in31;
assign	out31 = x31^in11^in21^in01;
assign	out02 = x02^in22^in32^in12;
assign	out12 = x12^in02^in32^in22;
assign	out22 = x22^in02^in12^in32;
assign	out32 = x32^in12^in22^in02;
assign	out03 = x03^in23^in33^in13;
assign	out13 = x13^in03^in33^in23;
assign	out23 = x23^in03^in13^in33;
assign	out33 = x33^in13^in23^in03;

endmodule


module xtime(xin, xout);		//xtime(02)
input	[7:0]xin;
output	[7:0]xout;

	assign	xout = xin[7]?((xin<<1)^8'H1B):(xin<<1);
	
endmodule