encryption.v

使用Verilog HDL 實現AES硬體加解密

module encryption (	clk,
					sel,
					clken_sb,
					data_in,
					key_in,
					data_out,
					final_out,
				  );

parameter AES_length = 128;
parameter AES_Round = 10;

input	clk, sel, clken_sb;
input	[AES_length-1:0] data_in;
input	[AES_length-1:0] key_in;

output	final_out;
output	[AES_length-1:0] data_out;

reg		final_out;
reg		[3:0] i;
reg		[AES_length-1:0] data_out;

wire	[AES_length-1:0] 	Sel_1, Sel_2, Sel_out,
							ShiftRow_out, MixColumn_out, SubBytes_out, u2_out;

wire	clk_not;

assign	clk_not = ~clk;						
assign	Sel_out = sel?Sel_2:Sel_1;

always @(posedge clk)
begin
	if(!sel)
	begin
		i = 0;
		final_out = 0;
	end
	
	else
	begin
		if (i <= AES_Round)
			i = i + 1;
		
		if (i == AES_Round)
		begin
			data_out = u2_out;
			final_out = 1;
		end
		
		else
			final_out = 0;
	end
end

AddRoundKey	u1(.data_in(data_in), .data_out(Sel_1), .key_in(key_in));
AddRoundKey	u2(.data_in(ShiftRow_out), .data_out(u2_out), .key_in(key_in));
AddRoundKey	u3(.data_in(MixColumn_out), .data_out(Sel_2), .key_in(key_in));
SubBytes	u4(.clk(clk_not), .clk_enable(clken_sb), .data_in(Sel_out), .data_out(SubBytes_out));
ShiftRow	u5(.data_in(SubBytes_out), .data_out(ShiftRow_out));
MixColumn	u6(.data_in(ShiftRow_out), .data_out(MixColumn_out));

endmodule