addroundkey.v

来自「使用Verilog HDL 實現AES硬體加解密」· Verilog 代码 · 共 16 行

module AddRoundKey (data_in, data_out, key_in);

parameter AES_length = 128;

input	[AES_length-1:0] data_in;
input	[AES_length-1:0] key_in;

output	[AES_length-1:0] data_out;

//AddRoundKey
assign	data_out = data_in ^ key_in;

endmodule