up3_clock.sim.rpt

在UP3开发板上已经验证过的VHDL代码。精确到十分之一秒

Please use Quartus II to view the waveform report data.


+--------------------------------------------------------------------+
; Coverage Summary                                                   ;
+-----------------------------------------------------+--------------+
; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;      32.60 % ;
; Total nodes checked                                 ; 1808         ;
; Total output ports checked                          ; 1908         ;
; Total output ports with complete 1/0-value coverage ; 622          ;
; Total output ports with no 1/0-value coverage       ; 1274         ;
; Total output ports with no 1-value coverage         ; 1281         ;
; Total output ports with no 0-value coverage         ; 1279         ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                                                       ;
+-----------------------------------------------------------------------------+----------------------------------------------------------------------------------+------------------+
; Node Name                                                                   ; Output Port Name                                                                 ; Output Port Type ;
+-----------------------------------------------------------------------------+----------------------------------------------------------------------------------+------------------+
; |UP3_CLOCK|CLK_COUNT_400HZ~13                                               ; |UP3_CLOCK|CLK_COUNT_400HZ~13                                                    ; out              ;
; |UP3_CLOCK|CLK_COUNT_400HZ~14                                               ; |UP3_CLOCK|CLK_COUNT_400HZ~14                                                    ; out              ;
; |UP3_CLOCK|CLK_COUNT_400HZ~15                                               ; |UP3_CLOCK|CLK_COUNT_400HZ~15                                                    ; out              ;
; |UP3_CLOCK|CLK_COUNT_400HZ~16                                               ; |UP3_CLOCK|CLK_COUNT_400HZ~16                                                    ; out              ;
; |UP3_CLOCK|CLK_COUNT_400HZ~17                                               ; |UP3_CLOCK|CLK_COUNT_400HZ~17                                                    ; out              ;
; |UP3_CLOCK|CLK_COUNT_400HZ~18                                               ; |UP3_CLOCK|CLK_COUNT_400HZ~18                                                    ; out              ;
; |UP3_CLOCK|CLK_COUNT_400HZ~19                                               ; |UP3_CLOCK|CLK_COUNT_400HZ~19                                                    ; out              ;
; |UP3_CLOCK|CLK_COUNT_400HZ~33                                               ; |UP3_CLOCK|CLK_COUNT_400HZ~33                                                    ; out              ;
; |UP3_CLOCK|CLK_COUNT_400HZ~34                                               ; |UP3_CLOCK|CLK_COUNT_400HZ~34                                                    ; out              ;
; |UP3_CLOCK|CLK_COUNT_400HZ~35                                               ; |UP3_CLOCK|CLK_COUNT_400HZ~35                                                    ; out              ;
; |UP3_CLOCK|CLK_COUNT_400HZ~36                                               ; |UP3_CLOCK|CLK_COUNT_400HZ~36                                                    ; out              ;
; |UP3_CLOCK|CLK_COUNT_400HZ~37                                               ; |UP3_CLOCK|CLK_COUNT_400HZ~37                                                    ; out              ;
; |UP3_CLOCK|CLK_COUNT_400HZ~38                                               ; |UP3_CLOCK|CLK_COUNT_400HZ~38                                                    ; out              ;
; |UP3_CLOCK|CLK_COUNT_400HZ~39                                               ; |UP3_CLOCK|CLK_COUNT_400HZ~39                                                    ; out              ;
; |UP3_CLOCK|BCD_SECD1~0                                                      ; |UP3_CLOCK|BCD_SECD1~0                                                           ; out              ;
; |UP3_CLOCK|BCD_SECD1~1                                                      ; |UP3_CLOCK|BCD_SECD1~1                                                           ; out              ;
; |UP3_CLOCK|BCD_SECD1~2                                                      ; |UP3_CLOCK|BCD_SECD1~2                                                           ; out              ;
; |UP3_CLOCK|BCD_SECD1~3                                                      ; |UP3_CLOCK|BCD_SECD1~3                                                           ; out              ;
; |UP3_CLOCK|BCD_SECD0~0                                                      ; |UP3_CLOCK|BCD_SECD0~0                                                           ; out              ;
; |UP3_CLOCK|BCD_SECD0~1                                                      ; |UP3_CLOCK|BCD_SECD0~1                                                           ; out              ;
; |UP3_CLOCK|BCD_SECD0~2                                                      ; |UP3_CLOCK|BCD_SECD0~2                                                           ; out              ;
; |UP3_CLOCK|BCD_SECD0~3                                                      ; |UP3_CLOCK|BCD_SECD0~3                                                           ; out              ;
; |UP3_CLOCK|BCD_SECD1~5                                                      ; |UP3_CLOCK|BCD_SECD1~5                                                           ; out              ;
; |UP3_CLOCK|BCD_SECD1~6                                                      ; |UP3_CLOCK|BCD_SECD1~6                                                           ; out              ;
; |UP3_CLOCK|BCD_SECD1~7                                                      ; |UP3_CLOCK|BCD_SECD1~7                                                           ; out              ;
; |UP3_CLOCK|BCD_SECD0~4                                                      ; |UP3_CLOCK|BCD_SECD0~4                                                           ; out              ;
; |UP3_CLOCK|BCD_SECD0~5                                                      ; |UP3_CLOCK|BCD_SECD0~5                                                           ; out              ;
; |UP3_CLOCK|BCD_SECD0~6                                                      ; |UP3_CLOCK|BCD_SECD0~6                                                           ; out              ;
; |UP3_CLOCK|BCD_SECD0~7                                                      ; |UP3_CLOCK|BCD_SECD0~7                                                           ; out              ;
; |UP3_CLOCK|BCD_SECD1~9                                                      ; |UP3_CLOCK|BCD_SECD1~9                                                           ; out              ;
; |UP3_CLOCK|BCD_SECD1~10                                                     ; |UP3_CLOCK|BCD_SECD1~10                                                          ; out              ;
; |UP3_CLOCK|BCD_SECD1~11                                                     ; |UP3_CLOCK|BCD_SECD1~11                                                          ; out              ;
; |UP3_CLOCK|BCD_MIND0~7                                                      ; |UP3_CLOCK|BCD_MIND0~7                                                           ; out              ;
; |UP3_CLOCK|BCD_HRD0~7                                                       ; |UP3_CLOCK|BCD_HRD0~7                                                            ; out              ;
; |UP3_CLOCK|PB1_PulseOut                                                     ; |UP3_CLOCK|PB1_PulseOut                                                          ; out0             ;
; |UP3_CLOCK|count1~0                                                         ; |UP3_CLOCK|count1~0                                                              ; out              ;
; |UP3_CLOCK|count1~1                                                         ; |UP3_CLOCK|count1~1                                                              ; out              ;
; |UP3_CLOCK|count1~2                                                         ; |UP3_CLOCK|count1~2                                                              ; out              ;
; |UP3_CLOCK|count1~3                                                         ; |UP3_CLOCK|count1~3                                                              ; out              ;
; |UP3_CLOCK|count1~4                                                         ; |UP3_CLOCK|count1~4                                                              ; out              ;
; |UP3_CLOCK|count1~5                                                         ; |UP3_CLOCK|count1~5                                                              ; out              ;
; |UP3_CLOCK|count1~6                                                         ; |UP3_CLOCK|count1~6                                                              ; out              ;
; |UP3_CLOCK|count1~7                                                         ; |UP3_CLOCK|count1~7                                                              ; out              ;
; |UP3_CLOCK|count1~8                                                         ; |UP3_CLOCK|count1~8                                                              ; out              ;
; |UP3_CLOCK|count1~9                                                         ; |UP3_CLOCK|count1~9                                                              ; out              ;
; |UP3_CLOCK|count1~10                                                        ; |UP3_CLOCK|count1~10                                                             ; out              ;
; |UP3_CLOCK|count1~11                                                        ; |UP3_CLOCK|count1~11                                                             ; out              ;
; |UP3_CLOCK|count1~12                                                        ; |UP3_CLOCK|count1~12                                                             ; out              ;
; |UP3_CLOCK|count1~13                                                        ; |UP3_CLOCK|count1~13                                                             ; out              ;
; |UP3_CLOCK|count1~14                                                        ; |UP3_CLOCK|count1~14                                                             ; out              ;
; |UP3_CLOCK|count1~15                                                        ; |UP3_CLOCK|count1~15                                                             ; out              ;
; |UP3_CLOCK|count1~16                                                        ; |UP3_CLOCK|count1~16                                                             ; out              ;
; |UP3_CLOCK|count1~17                                                        ; |UP3_CLOCK|count1~17                                                             ; out              ;
; |UP3_CLOCK|count1~18                                                        ; |UP3_CLOCK|count1~18                                                             ; out              ;
; |UP3_CLOCK|count1~19                                                        ; |UP3_CLOCK|count1~19                                                             ; out              ;
; |UP3_CLOCK|count1~20                                                        ; |UP3_CLOCK|count1~20                                                             ; out              ;
; |UP3_CLOCK|count1~21                                                        ; |UP3_CLOCK|count1~21                                                             ; out              ;
; |UP3_CLOCK|count1~22                                                        ; |UP3_CLOCK|count1~22                                                             ; out              ;
; |UP3_CLOCK|count1~23                                                        ; |UP3_CLOCK|count1~23                                                             ; out              ;
; |UP3_CLOCK|count1~24                                                        ; |UP3_CLOCK|count1~24                                                             ; out              ;
; |UP3_CLOCK|count1~25                                                        ; |UP3_CLOCK|count1~25                                                             ; out              ;
; |UP3_CLOCK|count1~26                                                        ; |UP3_CLOCK|count1~26                                                             ; out              ;