bcdconv.sim.qmsg

来自「BCD编码的Verilog HDL程序」· QMSG 代码 · 共 7 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Simulator " "Info: Running Quartus II Simulator" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 190 1/28/2004 SJ Full Version " "Info: Version 4.0 Build 190 1/28/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Mar 13 20:22:07 2005 " "Info: Processing started: Sun Mar 13 20:22:07 2005" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sim --lower_priority --import_settings_files=on --export_settings_files=off BCDconv -c BCDconv " "Info: Command: quartus_sim --lower_priority --import_settings_files=on --export_settings_files=off BCDconv -c BCDconv" {  } {  } 0}
{ "Info" "ISIM_SIM_SIMULATION_COVERAGE" "     69.23 % " "Info: Simulation coverage is      69.23 %" {  } {  } 0}
{ "Info" "ISIM_SIM_NUMBER_OF_TRANSITION" "96 " "Info: Number of transitions in simulation is 96" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Simulator 0 s 0 s " "Info: Quartus II Simulator was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 13 20:22:08 2005 " "Info: Processing ended: Sun Mar 13 20:22:08 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}