de2_tv.fit.talkback.xml

本源码是用verilog编写控制LCD——使用Quartusii

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This XML file (created on Tue Jul 01 20:09:09 2008) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
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<talkback>
<ver>6.0</ver>
<schema>quartus_version_6.0_build_178.xsd</schema>
<license>
	<host_id>00581cf7ea5d</host_id>
	<nic_id>00581cf7ea5d</nic_id>
	<cdrive_id>1c93edea</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>6.0</version>
	<build>Build 178</build>
	<binary_type>32</binary_type>
	<module>quartus_fit</module>
	<edition>Full Version</edition>
	<eval>Licensed</eval>
	<compilation_end_time>Tue Jul 01 20:09:10 2008</compilation_end_time>
</tool>
<machine>
	<os>Windows XP</os>
	<cpu>
		<proc_count>2</proc_count>
		<cpu_freq units="MHz">1596</cpu_freq>
	</cpu>
	<ram units="MB">1016</ram>
</machine>
<project>F:/DE2_TV/DE2_TV</project>
<revision>DE2_TV</revision>
<compilation_summary>
	<flow_status>Successful - Tue Jul 01 20:09:08 2008</flow_status>
	<quartus_ii_version>6.0 Build 178 04/27/2006 SJ Full Version</quartus_ii_version>
	<revision_name>DE2_TV</revision_name>
	<top_level_entity_name>DE2_LCD</top_level_entity_name>
	<family>Cyclone II</family>
	<device>EP2C35F672C8</device>
	<timing_models>Final</timing_models>
	<met_timing_requirements>N/A</met_timing_requirements>
	<total_logic_elements>105 / 33,216 ( &lt; 1 % )</total_logic_elements>
	<total_registers>51</total_registers>
	<total_pins>101 / 475 ( 21 % )</total_pins>
	<total_virtual_pins>0</total_virtual_pins>
	<total_memory_bits>0 / 483,840 ( 0 % )</total_memory_bits>
	<embedded_multiplier_9_bit_elements>0 / 70 ( 0 % )</embedded_multiplier_9_bit_elements>
	<total_plls>0 / 4 ( 0 % )</total_plls>
</compilation_summary>
<resource_usage_summary>
	<rsc name="Total logic elements" util="1" max=" 33216 " type="int">105 </rsc>
	<rsc name="-- Combinational with no register" type="int">54</rsc>
	<rsc name="-- Register only" type="int">0</rsc>
	<rsc name="-- Combinational with a register" type="int">51</rsc>
	<rsc name="Logic element usage by number of LUT inputs" type="text"></rsc>
	<rsc name="-- 4 input functions" type="int">47</rsc>
	<rsc name="-- 3 input functions" type="int">19</rsc>
	<rsc name="-- &lt;=2 input functions" type="int">39</rsc>
	<rsc name="-- Register only" type="int">0</rsc>
	<rsc name="Logic elements by mode" type="text"></rsc>
	<rsc name="-- normal mode" type="int">80</rsc>
	<rsc name="-- arithmetic mode" type="int">25</rsc>
	<rsc name="Total registers" util="1" max=" 33216 " type="int">51 </rsc>
	<rsc name="Total LABs" util="1" max=" 2076 " type="int">7 </rsc>
	<rsc name="User inserted logic elements" type="int">0</rsc>
	<rsc name="Virtual pins" type="int">0</rsc>
	<rsc name="I/O pins" util="21" max=" 475 " type="int">101 </rsc>
	<rsc name="-- Clock pins" util="13" max=" 8 " type="int">1 </rsc>
	<rsc name="Global signals" type="int">2</rsc>
	<rsc name="M4Ks" util="0" max=" 105 " type="int">0 </rsc>
	<rsc name="Total memory bits" util="0" max=" 483840 " type="int">0 </rsc>
	<rsc name="Total RAM block bits" util="0" max=" 483840 " type="int">0 </rsc>
	<rsc name="Embedded Multiplier 9-bit elements" util="0" max=" 70 " type="int">0 </rsc>
	<rsc name="PLLs" util="0" max=" 4 " type="int">0 </rsc>
	<rsc name="Global clocks" util="13" max=" 16 " type="int">2 </rsc>
	<rsc name="Maximum fan-out node" type="text">KEY[0]</rsc>
	<rsc name="Maximum fan-out" type="int">51</rsc>
	<rsc name="Highest non-global fan-out signal" type="text">KEY[0]</rsc>
	<rsc name="Highest non-global fan-out" type="int">51</rsc>
	<rsc name="Total fan-out" type="int">546</rsc>
	<rsc name="Average fan-out" type="float">2.09</rsc>
</resource_usage_summary>
<control_signals>
	<row>
		<name>LCD_TEST:u1|WideOr0~50</name>
		<location>LCCOMB_X1_Y27_N24</location>
		<fan_out>9</fan_out>
		<usage>Latch enable</usage>
		<global>yes</global>
		<global_resource_used>Global clock</global_resource_used>
		<global_line_name>GCLK1</global_line_name>
	</row>
	<row>
		<name>OSC_50</name>
		<location>PIN_N2</location>
		<fan_out>51</fan_out>
		<usage>Clock</usage>
		<global>yes</global>
		<global_resource_used>Global clock</global_resource_used>
		<global_line_name>GCLK2</global_line_name>
	</row>
</control_signals>
<non_global_high_fan_out_signals>
	<row>
		<name>LCD_TEST:u1|LCD_Controller:u0|LCD_EN</name>
		<fan_out>2</fan_out>
	</row>
	<row>
		<name>LCD_TEST:u1|mLCD_RS</name>
		<fan_out>1</fan_out>
	</row>
	<row>
		<name>LCD_TEST:u1|LCD_Controller:u0|ST.01</name>
		<fan_out>3</fan_out>
	</row>
	<row>
		<name>LCD_TEST:u1|LCD_Controller:u0|ST.10</name>
		<fan_out>8</fan_out>
	</row>
	<row>
		<name>LCD_TEST:u1|LCD_Controller:u0|ST.00</name>
		<fan_out>3</fan_out>
	</row>
	<row>
		<name>LCD_TEST:u1|LCD_Controller:u0|Selector3~19</name>
		<fan_out>1</fan_out>
	</row>
	<row>
		<name>LCD_TEST:u1|LCD_Controller:u0|mStart</name>
		<fan_out>12</fan_out>
	</row>
	<row>
		<name>LCD_TEST:u1|LUT_INDEX[3]</name>
		<fan_out>20</fan_out>
	</row>
	<row>
		<name>LCD_TEST:u1|LUT_INDEX[4]</name>
		<fan_out>17</fan_out>
	</row>
	<row>
		<name>LCD_TEST:u1|LessThan0~71</name>
		<fan_out>1</fan_out>
	</row>
</non_global_high_fan_out_signals>
<interconnect_usage_summary>
	<rsc name="Local interconnects" util="1" max=" 33216 " type="int">77 </rsc>
	<rsc name="Block interconnects" util="1" max=" 94460 " type="int">94 </rsc>
	<rsc name="R4 interconnects" util="1" max=" 81294 " type="int">33 </rsc>
	<rsc name="R24 interconnects" util="1" max=" 3091 " type="int">3 </rsc>
	<rsc name="C4 interconnects" util="1" max=" 60840 " type="int">44 </rsc>
	<rsc name="C16 interconnects" util="0" max=" 3315 " type="int">0 </rsc>
	<rsc name="Global clocks" util="13" max=" 16 " type="int">2 </rsc>
	<rsc name="Direct links" util="1" max=" 94460 " type="int">18 </rsc>
</interconnect_usage_summary>
<mep_data>
	<command_line>quartus_fit --read_settings_files=off --write_settings_files=off DE2_TV -c DE2_TV</command_line>
</mep_data>
<software_data>
	<smart_recompile>off</smart_recompile>
</software_data>
<messages>
	<warning>Warning: Following 86 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results</warning>
	<warning>Warning: Following 8 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results</warning>
	<warning>Warning: Found 96 output pins without output pin load capacitance assignment</warning>
	<warning>Warning: Ignored locations or region assignments to the following nodes</warning>
	<warning>Warning: Node &quot;VGA_VS&quot; is assigned to location or region, but does not exist in design</warning>
	<info>Info: Generated suppressed messages file F:/DE2_TV/DE2_TV.fit.smsg</info>
	<info>Info: Quartus II Fitter was successful. 0 errors, 349 warnings</info>
	<info>Info: Elapsed time: 00:00:33</info>
	<info>Info: Processing ended: Tue Jul 01 20:09:08 2008</info>
	<info>Info: Pin LCD_RW has GND driving its datain port</info>
</messages>
<fitter_settings>
	<row>
		<option>Device</option>
		<setting>EP2C35F672C8</setting>
	</row>
	<row>
		<option>Use smart compilation</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Router Timing Optimization Level</option>
		<setting>Normal</setting>
		<default_value>Normal</default_value>
	</row>
	<row>
		<option>Placement Effort Multiplier</option>
		<setting>1.0</setting>
		<default_value>1.0</default_value>
	</row>
	<row>
		<option>Router Effort Multiplier</option>
		<setting>1.0</setting>
		<default_value>1.0</default_value>
	</row>
	<row>
		<option>Optimize Hold Timing</option>
		<setting>IO Paths and Minimum TPD Paths</setting>
		<default_value>IO Paths and Minimum TPD Paths</default_value>
	</row>
	<row>
		<option>Optimize Fast-Corner Timing</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>PowerPlay Power Optimization</option>
		<setting>Normal compilation</setting>
		<default_value>Normal compilation</default_value>
	</row>
	<row>
		<option>Optimize Timing</option>
		<setting>Normal compilation</setting>
		<default_value>Normal compilation</default_value>
	</row>
	<row>
		<option>Optimize IOC Register Placement for Timing</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Limit to One Fitting Attempt</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Final Placement Optimizations</option>
		<setting>Automatically</setting>
		<default_value>Automatically</default_value>
	</row>
	<row>
		<option>Fitter Aggressive Routability Optimizations</option>
		<setting>Automatically</setting>
		<default_value>Automatically</default_value>
	</row>
	<row>
		<option>Fitter Initial Placement Seed</option>
		<setting>1</setting>
		<default_value>1</default_value>
	</row>
	<row>
		<option>PCI I/O</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Weak Pull-Up Resistor</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Enable Bus-Hold Circuitry</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Auto Global Memory Control Signals</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Auto Packed Registers -- Stratix II/Cyclone II</option>
		<setting>Auto</setting>
		<default_value>Auto</default_value>
	</row>
	<row>
		<option>Auto Delay Chains</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Merge PLLs</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Ignore PLL Mode When Merging PLLs</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Fitter Effort</option>
		<setting>Auto Fit</setting>
		<default_value>Auto Fit</default_value>
	</row>
	<row>
		<option>Physical Synthesis Effort Level</option>
		<setting>Normal</setting>
		<default_value>Normal</default_value>
	</row>
	<row>
		<option>Auto Global Clock</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Global Register Control Signals</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Always Enable Input Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
</fitter_settings>
<fitter_device_options>
	<row>
		<option>Enable user-supplied start-up clock (CLKUSR)</option>
		<setting>Off</setting>
	</row>
	<row>
		<option>Enable device-wide reset (DEV_CLRn)</option>
		<setting>Off</setting>
	</row>
	<row>
		<option>Enable device-wide output enable (DEV_OE)</option>
		<setting>Off</setting>
	</row>
	<row>
		<option>Enable INIT_DONE output</option>
		<setting>Off</setting>
	</row>
	<row>
		<option>Configuration scheme</option>
		<setting>Active Serial</setting>
	</row>
	<row>
		<option>Error detection CRC</option>
		<setting>Off</setting>
	</row>
	<row>
		<option>Reserve ASDO pin after configuration.</option>
		<setting>As input tri-stated</setting>
	</row>
	<row>
		<option>Reserve all unused pins</option>
		<setting>As input tri-stated</setting>
	</row>
	<row>
		<option>Base pin-out file on sameframe device</option>
		<setting>Off</setting>
	</row>
</fitter_device_options>
<input_pins>
	<row>
		<name>KEY[0]</name>
		<pin__>G26</pin__>
		<i_o_bank>5</i_o_bank>
		<x_coordinate>65</x_coordinate>
		<y_coordinate>27</y_coordinate>
		<cell_number>1</cell_number>
		<combinational_fan_out>51</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<input_register>no</input_register>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<termination>Off</termination>
		<location_assigned_by>User</location_assigned_by>
	</row>
	<row>
		<name>KEY[1]</name>
		<pin__>N23</pin__>
		<i_o_bank>5</i_o_bank>
		<x_coordinate>65</x_coordinate>
		<y_coordinate>20</y_coordinate>
		<cell_number>2</cell_number>
		<combinational_fan_out>0</combinational_fan_out>
		<registered_fan_out>0</registered_fan_out>
		<global>no</global>
		<input_register>no</input_register>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<termination>Off</termination>
		<location_assigned_by>User</location_assigned_by>
	</row>
	<row>
		<name>KEY[2]</name>
		<pin__>P23</pin__>
		<i_o_bank>6</i_o_bank>
		<x_coordinate>65</x_coordinate>
		<y_coordinate>18</y_coordinate>