dds.map.summary

实现DDS频率可调得VHDL程序

Flow Status : Successful - Tue May 27 18:15:31 2008
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : DDS
Top-level Entity Name : DDS
Family : Cyclone
Device : EP1C3T144C8
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 9
Total pins : 19
Total virtual pins : 0
Total memory bits : 8,192
Total PLLs : 0