main.vhd

用VHDL实现频率计

-- MAX+plus II VHDL Template
-- Clearable flipflop with enable

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY main IS

	PORT
	(
		clk,FIN		: IN	STD_LOGIC;
		q0,q1,q2,q3	: OUT	STD_LOGIC_VECTOR(6 DOWNTO 0)
	);
	
END main;

ARCHITECTURE a OF main IS

COMPONENT cnt10 
PORT(		clk,rst,en	: IN	STD_LOGIC;
			CQ			: OUT	STD_LOGIC_VECTOR(3 DOWNTO 0);
			COUT		: OUT 	STD_LOGIC
	);
	
END COMPONENT;

COMPONENT BUFF  
PORT(		LD			: IN	STD_LOGIC;
			AA			: IN	STD_LOGIC_VECTOR(3 DOWNTO 0);
			BB			: OUT 	STD_LOGIC_VECTOR(3 DOWNTO 0)
	);
	
END COMPONENT;

COMPONENT contrOl  
PORT(		clk			: IN	STD_LOGIC;
			EN,LD,RST	: OUT 	STD_LOGIC
	);
	
END COMPONENT;

COMPONENT led 
port( 		datain		:IN std_logic_vector(3 downto 0);
			Dataout		:OUT std_logic_vector(6 downto 0)
	);

end COMPONENT;

SIGNAL EN1,clr1,ld1    	: STD_LOGIC;
SIGNAL co0,co1,co2,co3 	: STD_LOGIC;
SIGNAL cq0,cq1,cq2,cq3  : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL BQ0,BQ1,BQ2,BQ3  : STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN
U1: contrOl 	PorT  MAP (CLK,EN1,LD1,CLR1);

U2: CNT10 		PorT  MAP (FIN,CLR1,EN1,CQ0,CO0);
U3: CNT10 		PorT  MAP (CO0,CLR1,EN1,CQ1,CO1);
U4: CNT10 		PorT  MAP (CO1,CLR1,EN1,CQ2,CO2);
U5: CNT10 		PorT  MAP (CO2,CLR1,EN1,CQ3,CO3);

U6: BUFF 		PorT  MAP (LD1,CQ0,BQ0);
U7: BUFF 		PorT  MAP (LD1,CQ1,BQ1);
U8: BUFF 		PorT  MAP (LD1,CQ2,BQ2);
U9: BUFF 		PorT  MAP (LD1,CQ3,BQ3);

U10: LED 		PorT  MAP (BQ0,Q0);
U11: LED 		PorT  MAP (BQ1,Q1);
U12: LED 		PorT  MAP (BQ2,Q2);
U13: LED 		PorT  MAP (BQ3,Q3);
END A;