main.rpt

用VHDL实现频率计

 (55)    80    E       DFFE      t        0      0   0    0    5    7    0  |BUFF:U6|BUFF12 (|BUFF:U6|:11)
   -     76    E       DFFE      t        0      0   0    0    5    7    0  |BUFF:U6|BUFF11 (|BUFF:U6|:12)
 (54)    77    E       DFFE      t        0      0   0    0    5    7    0  |BUFF:U6|BUFF10 (|BUFF:U6|:13)
   -     83    F       DFFE      t        0      0   0    0    5    7    0  |BUFF:U7|BUFF13 (|BUFF:U7|:10)
 (56)    81    F       DFFE      t        0      0   0    0    5    7    0  |BUFF:U7|BUFF12 (|BUFF:U7|:11)
   -     95    F       DFFE      t        0      0   0    0    5    7    0  |BUFF:U7|BUFF11 (|BUFF:U7|:12)
 (57)    84    F       DFFE      t        0      0   0    0    5    7    0  |BUFF:U7|BUFF10 (|BUFF:U7|:13)
   -     66    E       DFFE      t        0      0   0    0    5    7    0  |BUFF:U8|BUFF13 (|BUFF:U8|:10)
   -     71    E       DFFE      t        0      0   0    0    5    7    0  |BUFF:U8|BUFF12 (|BUFF:U8|:11)
   -     70    E       DFFE      t        0      0   0    0    5    7    0  |BUFF:U8|BUFF11 (|BUFF:U8|:12)
   -     68    E       DFFE      t        0      0   0    0    5    7    0  |BUFF:U8|BUFF10 (|BUFF:U8|:13)
 (47)    67    E       DFFE      t        0      0   0    0    5    7    0  |BUFF:U9|BUFF13 (|BUFF:U9|:10)
 (46)    65    E       DFFE      t        0      0   0    0    5    7    0  |BUFF:U9|BUFF12 (|BUFF:U9|:11)
 (52)    75    E       DFFE      t        0      0   0    0    5    7    0  |BUFF:U9|BUFF11 (|BUFF:U9|:12)
 (50)    72    E       DFFE      t        0      0   0    0    5    7    0  |BUFF:U9|BUFF10 (|BUFF:U9|:13)
 (59)    86    F       DFFE      t        2      0   1    1    9    0    9  |cnt10:U2|CQI3 (|cnt10:U2|:11)
 (60)    88    F       TFFE      t        1      0   1    1    9    0    8  |cnt10:U2|CQI2 (|cnt10:U2|:12)
 (61)    89    F       DFFE      t        1      0   1    1    8    0    9  |cnt10:U2|CQI1 (|cnt10:U2|:13)
   -     87    F       DFFE      t        1      0   1    1    9    0    9  |cnt10:U2|CQI0 (|cnt10:U2|:14)
 (65)    96    F       DFFE      t        2      0   1    0   13    0    9  |cnt10:U3|CQI3 (|cnt10:U3|:11)
 (64)    94    F       TFFE      t        1      0   1    0   13    0    8  |cnt10:U3|CQI2 (|cnt10:U3|:12)
 (62)    92    F       DFFE      t        1      0   1    0   12    0    9  |cnt10:U3|CQI1 (|cnt10:U3|:13)
   -     93    F       DFFE      t        1      0   1    0   13    0    9  |cnt10:U3|CQI0 (|cnt10:U3|:14)
   -     91    F       DFFE      t        2      0   1    0   13    0    9  |cnt10:U4|CQI3 (|cnt10:U4|:11)
   -     85    F       TFFE      t        1      0   1    0   13    0    8  |cnt10:U4|CQI2 (|cnt10:U4|:12)
   -     82    F       DFFE      t        1      0   1    0   12    0    9  |cnt10:U4|CQI1 (|cnt10:U4|:13)
   -     90    F       DFFE      t        1      0   1    0   13    0    9  |cnt10:U4|CQI0 (|cnt10:U4|:14)
   -     78    E       DFFE      t        2      0   1    0   13    0    5  |cnt10:U5|CQI3 (|cnt10:U5|:11)
 (51)    73    E       TFFE      t        1      0   1    0   13    0    4  |cnt10:U5|CQI2 (|cnt10:U5|:12)
   -     79    E       DFFE      t        1      0   1    0   12    0    5  |cnt10:U5|CQI1 (|cnt10:U5|:13)
   -     74    E       DFFE      t        1      0   1    0   13    0    5  |cnt10:U5|CQI0 (|cnt10:U5|:14)
 (40)    56    D       DFFE   +  t        0      0   0    0    1    0   16  |contrOl:U1|:2
   -     52    D       TFFE   +  t        0      0   0    0    3    0   33  |contrOl:U1|Q3 (|contrOl:U1|:6)
   -     54    D       TFFE   +  t        0      0   0    0    2    0   33  |contrOl:U1|Q2 (|contrOl:U1|:7)
   -     55    D       TFFE   +  t        0      0   0    0    1    0   34  |contrOl:U1|Q1 (|contrOl:U1|:8)
   -     50    D       TFFE   +  t        0      0   0    0    0    0   35  |contrOl:U1|Q0 (|contrOl:U1|:9)


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                                 d:\frudh\main.rpt
main

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'A':

                       Logic cells placed in LAB 'A'
        +------------- LC16 q30
        | +----------- LC14 q31
        | | +--------- LC12 q32
        | | | +------- LC9 q33
        | | | | +----- LC8 q34
        | | | | | +--- LC6 q35
        | | | | | | +- LC4 q36
        | | | | | | | 
        | | | | | | |   Other LABs fed by signals
        | | | | | | |   that feed LAB 'A'
LC      | | | | | | | | A B C D E F |     Logic cells that feed LAB 'A':

Pin
67   -> - - - - - - - | - - - - - - | <-- clk
LC67 -> * * * * * * * | * - - - - - | <-- |BUFF:U9|BUFF13
LC65 -> * * * * * * * | * - - - - - | <-- |BUFF:U9|BUFF12
LC75 -> * * * * * * * | * - - - - - | <-- |BUFF:U9|BUFF11
LC72 -> * * * * * * * | * - - - - - | <-- |BUFF:U9|BUFF10


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                 d:\frudh\main.rpt
main

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                       Logic cells placed in LAB 'B'
        +------------- LC29 q20
        | +----------- LC27 q21
        | | +--------- LC25 q22
        | | | +------- LC24 q23
        | | | | +----- LC21 q24
        | | | | | +--- LC19 q25
        | | | | | | +- LC17 q26
        | | | | | | | 
        | | | | | | |   Other LABs fed by signals
        | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | A B C D E F |     Logic cells that feed LAB 'B':

Pin
67   -> - - - - - - - | - - - - - - | <-- clk
LC66 -> * * * * * * * | - * - - - - | <-- |BUFF:U8|BUFF13
LC71 -> * * * * * * * | - * - - - - | <-- |BUFF:U8|BUFF12
LC70 -> * * * * * * * | - * - - - - | <-- |BUFF:U8|BUFF11
LC68 -> * * * * * * * | - * - - - - | <-- |BUFF:U8|BUFF10


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                 d:\frudh\main.rpt
main

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'C':

                       Logic cells placed in LAB 'C'
        +------------- LC35 q10
        | +----------- LC33 q11
        | | +--------- LC41 q12
        | | | +------- LC43 q13
        | | | | +----- LC45 q14
        | | | | | +--- LC37 q15
        | | | | | | +- LC40 q16
        | | | | | | | 
        | | | | | | |   Other LABs fed by signals
        | | | | | | |   that feed LAB 'C'
LC      | | | | | | | | A B C D E F |     Logic cells that feed LAB 'C':

Pin
67   -> - - - - - - - | - - - - - - | <-- clk
LC83 -> * * * * * * * | - - * - - - | <-- |BUFF:U7|BUFF13
LC81 -> * * * * * * * | - - * - - - | <-- |BUFF:U7|BUFF12
LC95 -> * * * * * * * | - - * - - - | <-- |BUFF:U7|BUFF11
LC84 -> * * * * * * * | - - * - - - | <-- |BUFF:U7|BUFF10


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                 d:\frudh\main.rpt
main

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'D':

                                 Logic cells placed in LAB 'D'
        +----------------------- LC56 |contrOl:U1|:2
        | +--------------------- LC52 |contrOl:U1|Q3
        | | +------------------- LC54 |contrOl:U1|Q2
        | | | +----------------- LC55 |contrOl:U1|Q1
        | | | | +--------------- LC50 |contrOl:U1|Q0
        | | | | | +------------- LC51 q00
        | | | | | | +----------- LC49 q01
        | | | | | | | +--------- LC64 q02
        | | | | | | | | +------- LC59 q03
        | | | | | | | | | +----- LC57 q04
        | | | | | | | | | | +--- LC53 q05
        | | | | | | | | | | | +- LC61 q06
        | | | | | | | | | | | | 
        | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | |   that feed LAB 'D'
LC      | | | | | | | | | | | | | A B C D E F |     Logic cells that feed LAB 'D':
LC52 -> * * - - - - - - - - - - | - - - * * * | <-- |contrOl:U1|Q3
LC54 -> - * * - - - - - - - - - | - - - * * * | <-- |contrOl:U1|Q2
LC55 -> - * * * - - - - - - - - | - - - * * * | <-- |contrOl:U1|Q1
LC50 -> - * * * * - - - - - - - | - - - * * * | <-- |contrOl:U1|Q0

Pin
67   -> - - - - - - - - - - - - | - - - - - - | <-- clk
LC69 -> - - - - - * * * * * * * | - - - * - - | <-- |BUFF:U6|BUFF13
LC80 -> - - - - - * * * * * * * | - - - * - - | <-- |BUFF:U6|BUFF12
LC76 -> - - - - - * * * * * * * | - - - * - - | <-- |BUFF:U6|BUFF11
LC77 -> - - - - - * * * * * * * | - - - * - - | <-- |BUFF:U6|BUFF10


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                 d:\frudh\main.rpt
main

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'E':

                                         Logic cells placed in LAB 'E'
        +------------------------------- LC69 |BUFF:U6|BUFF13
        | +----------------------------- LC80 |BUFF:U6|BUFF12
        | | +--------------------------- LC76 |BUFF:U6|BUFF11
        | | | +------------------------- LC77 |BUFF:U6|BUFF10
        | | | | +----------------------- LC66 |BUFF:U8|BUFF13
        | | | | | +--------------------- LC71 |BUFF:U8|BUFF12
        | | | | | | +------------------- LC70 |BUFF:U8|BUFF11
        | | | | | | | +----------------- LC68 |BUFF:U8|BUFF10
        | | | | | | | | +--------------- LC67 |BUFF:U9|BUFF13
        | | | | | | | | | +------------- LC65 |BUFF:U9|BUFF12
        | | | | | | | | | | +----------- LC75 |BUFF:U9|BUFF11
        | | | | | | | | | | | +--------- LC72 |BUFF:U9|BUFF10
        | | | | | | | | | | | | +------- LC78 |cnt10:U5|CQI3
        | | | | | | | | | | | | | +----- LC73 |cnt10:U5|CQI2
        | | | | | | | | | | | | | | +--- LC79 |cnt10:U5|CQI1
        | | | | | | | | | | | | | | | +- LC74 |cnt10:U5|CQI0
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'E'
LC      | | | | | | | | | | | | | | | | | A B C D E F |     Logic cells that feed LAB 'E':
LC78 -> - - - - - - - - * - - - * * * * | - - - - * - | <-- |cnt10:U5|CQI3
LC73 -> - - - - - - - - - * - - * * - * | - - - - * - | <-- |cnt10:U5|CQI2
LC79 -> - - - - - - - - - - * - * * * * | - - - - * - | <-- |cnt10:U5|CQI1
LC74 -> - - - - - - - - - - - * * * * * | - - - - * - | <-- |cnt10:U5|CQI0

Pin
67   -> - - - - - - - - - - - - - - - - | - - - - - - | <-- clk
LC86 -> * - - - - - - - - - - - - - - - | - - - - * * | <-- |cnt10:U2|CQI3
LC88 -> - * - - - - - - - - - - - - - - | - - - - * * | <-- |cnt10:U2|CQI2
LC89 -> - - * - - - - - - - - - - - - - | - - - - * * | <-- |cnt10:U2|CQI1
LC87 -> - - - * - - - - - - - - - - - - | - - - - * * | <-- |cnt10:U2|CQI0
LC91 -> - - - - * - - - - - - - * * * * | - - - - * * | <-- |cnt10:U4|CQI3
LC85 -> - - - - - * - - - - - - * * * * | - - - - * * | <-- |cnt10:U4|CQI2
LC82 -> - - - - - - * - - - - - * * * * | - - - - * * | <-- |cnt10:U4|CQI1
LC90 -> - - - - - - - * - - - - * * * * | - - - - * * | <-- |cnt10:U4|CQI0
LC56 -> - - - - - - - - - - - - * * * * | - - - - * * | <-- |contrOl:U1|:2
LC52 -> * * * * * * * * * * * * * * * * | - - - * * * | <-- |contrOl:U1|Q3
LC54 -> * * * * * * * * * * * * * * * * | - - - * * * | <-- |contrOl:U1|Q2
LC55 -> * * * * * * * * * * * * * * * * | - - - * * * | <-- |contrOl:U1|Q1
LC50 -> * * * * * * * * * * * * * * * * | - - - * * * | <-- |contrOl:U1|Q0


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                 d:\frudh\main.rpt
main

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'F':

                                         Logic cells placed in LAB 'F'
        +------------------------------- LC83 |BUFF:U7|BUFF13
        | +----------------------------- LC81 |BUFF:U7|BUFF12
        | | +--------------------------- LC95 |BUFF:U7|BUFF11
        | | | +------------------------- LC84 |BUFF:U7|BUFF10
        | | | | +----------------------- LC86 |cnt10:U2|CQI3
        | | | | | +--------------------- LC88 |cnt10:U2|CQI2
        | | | | | | +------------------- LC89 |cnt10:U2|CQI1
        | | | | | | | +----------------- LC87 |cnt10:U2|CQI0
        | | | | | | | | +--------------- LC96 |cnt10:U3|CQI3
        | | | | | | | | | +------------- LC94 |cnt10:U3|CQI2
        | | | | | | | | | | +----------- LC92 |cnt10:U3|CQI1
        | | | | | | | | | | | +--------- LC93 |cnt10:U3|CQI0
        | | | | | | | | | | | | +------- LC91 |cnt10:U4|CQI3
        | | | | | | | | | | | | | +----- LC85 |cnt10:U4|CQI2
        | | | | | | | | | | | | | | +--- LC82 |cnt10:U4|CQI1
        | | | | | | | | | | | | | | | +- LC90 |cnt10:U4|CQI0
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'F'
LC      | | | | | | | | | | | | | | | | | A B C D E F |     Logic cells that feed LAB 'F':
LC86 -> - - - - * * * * * * * * - - - - | - - - - * * | <-- |cnt10:U2|CQI3
LC88 -> - - - - * * - * * * * * - - - - | - - - - * * | <-- |cnt10:U2|CQI2
LC89 -> - - - - * * * * * * * * - - - - | - - - - * * | <-- |cnt10:U2|CQI1
LC87 -> - - - - * * * * * * * * - - - - | - - - - * * | <-- |cnt10:U2|CQI0
LC96 -> * - - - - - - - * * * * * * * * | - - - - - * | <-- |cnt10:U3|CQI3
LC94 -> - * - - - - - - * * - * * * * * | - - - - - * | <-- |cnt10:U3|CQI2
LC92 -> - - * - - - - - * * * * * * * * | - - - - - * | <-- |cnt10:U3|CQI1
LC93 -> - - - * - - - - * * * * * * * * | - - - - - * | <-- |cnt10:U3|CQI0
LC91 -> - - - - - - - - - - - - * * * * | - - - - * * | <-- |cnt10:U4|CQI3
LC85 -> - - - - - - - - - - - - * * - * | - - - - * * | <-- |cnt10:U4|CQI2
LC82 -> - - - - - - - - - - - - * * * * | - - - - * * | <-- |cnt10:U4|CQI1
LC90 -> - - - - - - - - - - - - * * * * | - - - - * * | <-- |cnt10:U4|CQI0

Pin
67   -> - - - - - - - - - - - - - - - - | - - - - - - | <-- clk
13   -> - - - - * * * * - - - - - - - - | - - - - - * | <-- FIN
LC56 -> - - - - * * * * * * * * * * * * | - - - - * * | <-- |contrOl:U1|:2
LC52 -> * * * * * * * * * * * * * * * * | - - - * * * | <-- |contrOl:U1|Q3
LC54 -> * * * * * * * * * * * * * * * * | - - - * * * | <-- |contrOl:U1|Q2
LC55 -> * * * * * * * * * * * * * * * * | - - - * * * | <-- |contrOl:U1|Q1
LC50 -> * * * * * * * * * * * * * * * * | - - - * * * | <-- |contrOl:U1|Q0