📄 main.rpt
字号:
Project Information d:\frudh\main.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 06/08/2008 20:32:23
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
MAIN
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
main EPM7096LC68-7 2 28 0 65 4 67 %
User Pins: 2 28 0
Project Information d:\frudh\main.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'clk' chosen for auto global Clock
Project Information d:\frudh\main.rpt
** FILE HIERARCHY **
|control:U1|
|control:U1|lpm_add_sub:28|
|control:U1|lpm_add_sub:28|addcore:adder|
|control:U1|lpm_add_sub:28|addcore:adder|addcore:adder0|
|control:U1|lpm_add_sub:28|altshift:result_ext_latency_ffs|
|control:U1|lpm_add_sub:28|altshift:carry_ext_latency_ffs|
|control:U1|lpm_add_sub:28|altshift:oflow_ext_latency_ffs|
|cnt10:U2|
|cnt10:U2|lpm_add_sub:52|
|cnt10:U2|lpm_add_sub:52|addcore:adder|
|cnt10:U2|lpm_add_sub:52|addcore:adder|addcore:adder0|
|cnt10:U2|lpm_add_sub:52|altshift:result_ext_latency_ffs|
|cnt10:U2|lpm_add_sub:52|altshift:carry_ext_latency_ffs|
|cnt10:U2|lpm_add_sub:52|altshift:oflow_ext_latency_ffs|
|cnt10:U3|
|cnt10:U3|lpm_add_sub:52|
|cnt10:U3|lpm_add_sub:52|addcore:adder|
|cnt10:U3|lpm_add_sub:52|addcore:adder|addcore:adder0|
|cnt10:U3|lpm_add_sub:52|altshift:result_ext_latency_ffs|
|cnt10:U3|lpm_add_sub:52|altshift:carry_ext_latency_ffs|
|cnt10:U3|lpm_add_sub:52|altshift:oflow_ext_latency_ffs|
|cnt10:U4|
|cnt10:U4|lpm_add_sub:52|
|cnt10:U4|lpm_add_sub:52|addcore:adder|
|cnt10:U4|lpm_add_sub:52|addcore:adder|addcore:adder0|
|cnt10:U4|lpm_add_sub:52|altshift:result_ext_latency_ffs|
|cnt10:U4|lpm_add_sub:52|altshift:carry_ext_latency_ffs|
|cnt10:U4|lpm_add_sub:52|altshift:oflow_ext_latency_ffs|
|cnt10:U5|
|cnt10:U5|lpm_add_sub:52|
|cnt10:U5|lpm_add_sub:52|addcore:adder|
|cnt10:U5|lpm_add_sub:52|addcore:adder|addcore:adder0|
|cnt10:U5|lpm_add_sub:52|altshift:result_ext_latency_ffs|
|cnt10:U5|lpm_add_sub:52|altshift:carry_ext_latency_ffs|
|cnt10:U5|lpm_add_sub:52|altshift:oflow_ext_latency_ffs|
|buff:U6|
|buff:U7|
|buff:U8|
|buff:U9|
|led:U10|
|led:U11|
|led:U12|
|led:U13|
Device-Specific Information: d:\frudh\main.rpt
main
***** Logic for device 'main' compiled without errors.
Device: EPM7096LC68-7
Device Options:
Turbo Bit = ON
Security Bit = OFF
MultiVolt I/O = OFF
R R R R
E E E E
V S S S S
C E E V E E
C R R C R R
q q q G q q I G G G c G V V C V V
3 3 3 N 3 3 N N N N l N E E I E E
4 3 2 D 1 0 T D D D k D D D O D D
-----------------------------------------------------_
/ 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 |
q35 | 10 60 | RESERVED
VCCIO | 11 59 | RESERVED
q36 | 12 58 | GND
FIN | 13 57 | RESERVED
RESERVED | 14 56 | RESERVED
q20 | 15 55 | RESERVED
GND | 16 54 | RESERVED
q21 | 17 53 | VCCIO
q22 | 18 EPM7096LC68-7 52 | RESERVED
q23 | 19 51 | RESERVED
q24 | 20 50 | RESERVED
VCCIO | 21 49 | RESERVED
q25 | 22 48 | GND
q26 | 23 47 | RESERVED
RESERVED | 24 46 | RESERVED
q14 | 25 45 | q02
GND | 26 44 | q06
|_ 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 _|
------------------------------------------------------
q q q q V q q G V q q G q R q q V
1 1 1 1 C 1 1 N C 0 0 N 0 E 0 0 C
3 2 6 5 C 0 1 D C 1 0 D 5 S 4 3 C
I I E I
O N R O
T V
E
D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: d:\frudh\main.rpt
main
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 7/16( 43%) 8/ 8(100%) 0/16( 0%) 4/36( 11%)
B: LC17 - LC32 7/16( 43%) 7/ 8( 87%) 0/16( 0%) 4/36( 11%)
C: LC33 - LC48 7/16( 43%) 7/ 8( 87%) 0/16( 0%) 4/36( 11%)
D: LC49 - LC64 12/16( 75%) 7/ 8( 87%) 0/16( 0%) 8/36( 22%)
E: LC65 - LC80 16/16(100%) 0/ 8( 0%) 5/16( 31%) 17/36( 47%)
F: LC81 - LC96 16/16(100%) 0/ 8( 0%) 15/16( 93%) 18/36( 50%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 29/48 ( 60%)
Total logic cells used: 65/96 ( 67%)
Total shareable expanders used: 4/96 ( 4%)
Total Turbo logic cells used: 65/96 ( 67%)
Total shareable expanders not available (n/a): 16/96 ( 16%)
Average fan-in: 6.15
Total fan-in: 400
Total input pins required: 2
Total output pins required: 28
Total bidirectional pins required: 0
Total logic cells required: 65
Total flipflops required: 37
Total product terms required: 221
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 4
Synthesized logic cells: 0/ 96 ( 0%)
Device-Specific Information: d:\frudh\main.rpt
main
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
67 - - INPUT G 0 0 0 0 0 0 0 clk
13 (1) (A) INPUT 0 0 0 0 0 0 4 FIN
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\frudh\main.rpt
main
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
37 51 D OUTPUT t 0 0 0 0 4 0 0 q00
36 49 D OUTPUT t 0 0 0 0 4 0 0 q01
45 64 D OUTPUT t 0 0 0 0 4 0 0 q02
42 59 D OUTPUT t 0 0 0 0 4 0 0 q03
41 57 D OUTPUT t 0 0 0 0 4 0 0 q04
39 53 D OUTPUT t 0 0 0 0 4 0 0 q05
44 61 D OUTPUT t 0 0 0 0 4 0 0 q06
32 35 C OUTPUT t 0 0 0 0 4 0 0 q10
33 33 C OUTPUT t 0 0 0 0 4 0 0 q11
28 41 C OUTPUT t 0 0 0 0 4 0 0 q12
27 43 C OUTPUT t 0 0 0 0 4 0 0 q13
25 45 C OUTPUT t 0 0 0 0 4 0 0 q14
30 37 C OUTPUT t 0 0 0 0 4 0 0 q15
29 40 C OUTPUT t 0 0 0 0 4 0 0 q16
15 29 B OUTPUT t 0 0 0 0 4 0 0 q20
17 27 B OUTPUT t 0 0 0 0 4 0 0 q21
18 25 B OUTPUT t 0 0 0 0 4 0 0 q22
19 24 B OUTPUT t 0 0 0 0 4 0 0 q23
20 21 B OUTPUT t 0 0 0 0 4 0 0 q24
22 19 B OUTPUT t 0 0 0 0 4 0 0 q25
23 17 B OUTPUT t 0 0 0 0 4 0 0 q26
4 16 A OUTPUT t 0 0 0 0 4 0 0 q30
5 14 A OUTPUT t 0 0 0 0 4 0 0 q31
7 12 A OUTPUT t 0 0 0 0 4 0 0 q32
8 9 A OUTPUT t 0 0 0 0 4 0 0 q33
9 8 A OUTPUT t 0 0 0 0 4 0 0 q34
10 6 A OUTPUT t 0 0 0 0 4 0 0 q35
12 4 A OUTPUT t 0 0 0 0 4 0 0 q36
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\frudh\main.rpt
main
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(49) 69 E DFFE t 0 0 0 0 5 7 0 |BUFF:U6|BUFF13 (|BUFF:U6|:10)
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -