📄 cnts.rpt
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Device-Specific Information: c:\maxplus2\verilog6\cnts.rpt
cnts
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 5 mclk
Device-Specific Information: c:\maxplus2\verilog6\cnts.rpt
cnts
** EQUATIONS **
en : INPUT;
mclk : INPUT;
-- Node name is 'cq0'
-- Equation name is 'cq0', type is output
cq0 = _LC6_E34;
-- Node name is 'cq1'
-- Equation name is 'cq1', type is output
cq1 = _LC5_E34;
-- Node name is 'cq2'
-- Equation name is 'cq2', type is output
cq2 = _LC8_E34;
-- Node name is 'cq3'
-- Equation name is 'cq3', type is output
cq3 = _LC7_E34;
-- Node name is 's10s'
-- Equation name is 's10s', type is output
s10s = _LC1_E34;
-- Node name is '|lpm_add_sub:64|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_E34', type is buried
_LC3_E34 = LCELL( _EQ001);
_EQ001 = _LC5_E34 & _LC6_E34;
-- Node name is '|lpm_add_sub:64|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_E34', type is buried
_LC4_E34 = LCELL( _EQ002);
_EQ002 = _LC5_E34 & _LC6_E34 & _LC8_E34;
-- Node name is ':9'
-- Equation name is '_LC2_E34', type is buried
!_LC2_E34 = _LC2_E34~NOT;
_LC2_E34~NOT = LCELL( _EQ003);
_EQ003 = !_LC6_E34
# _LC8_E34
# !_LC7_E34
# _LC5_E34;
-- Node name is ':48'
-- Equation name is '_LC7_E34', type is buried
_LC7_E34 = DFFE( _EQ004, GLOBAL(!mclk), VCC, VCC, VCC);
_EQ004 = !_LC2_E34 & !_LC4_E34 & _LC7_E34
# en & !_LC2_E34 & _LC4_E34 & !_LC7_E34
# !en & _LC7_E34;
-- Node name is ':49'
-- Equation name is '_LC8_E34', type is buried
_LC8_E34 = DFFE( _EQ005, GLOBAL(!mclk), VCC, VCC, VCC);
_EQ005 = !_LC2_E34 & !_LC3_E34 & _LC8_E34
# en & !_LC2_E34 & _LC3_E34 & !_LC8_E34
# !en & _LC8_E34;
-- Node name is ':50'
-- Equation name is '_LC5_E34', type is buried
_LC5_E34 = DFFE( _EQ006, GLOBAL(!mclk), VCC, VCC, VCC);
_EQ006 = !_LC2_E34 & _LC5_E34 & !_LC6_E34
# en & !_LC2_E34 & !_LC5_E34 & _LC6_E34
# !en & _LC5_E34;
-- Node name is ':51'
-- Equation name is '_LC6_E34', type is buried
_LC6_E34 = DFFE( _EQ007, GLOBAL(!mclk), VCC, VCC, VCC);
_EQ007 = !en & _LC6_E34
# en & !_LC6_E34;
-- Node name is ':63'
-- Equation name is '_LC1_E34', type is buried
_LC1_E34 = DFFE( _EQ008, GLOBAL(!mclk), VCC, VCC, VCC);
_EQ008 = !_LC5_E34 & _LC6_E34 & _LC7_E34 & !_LC8_E34;
Project Information c:\maxplus2\verilog6\cnts.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:09
Timing SNF Extractor 00:00:01
Assembler 00:00:03
-------------------------- --------
Total Time 00:00:14
Memory Allocated
-----------------
Peak memory allocated during compilation = 51,125K
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