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📄 div.rpt

📁 verilog除頻器可用於編碼段運用可以穩定電路設計
💻 RPT
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  _EQ011 = !_LC5_A38 & !_LC7_A36 &  Q10
         # !_LC5_A38 &  _LC7_A36 & !Q10;

-- Node name is ':80' = 'Q11' 
-- Equation name is 'Q11', location is LC3_A28, type is buried.
Q11      = DFFE( _EQ012, GLOBAL( CLKI),  VCC,  VCC,  VCC);
  _EQ012 = !_LC5_A38 & !_LC8_A36 &  Q11
         # !_LC5_A38 &  _LC8_A36 & !Q11;

-- Node name is ':79' = 'Q12' 
-- Equation name is 'Q12', location is LC8_A34, type is buried.
Q12      = DFFE( _EQ013, GLOBAL( CLKI),  VCC,  VCC,  VCC);
  _EQ013 = !_LC5_A38 & !Q11 &  Q12
         # !_LC5_A38 & !_LC8_A36 &  Q12
         # !_LC5_A38 &  _LC8_A36 &  Q11 & !Q12;

-- Node name is ':78' = 'Q13' 
-- Equation name is 'Q13', location is LC6_A34, type is buried.
Q13      = DFFE( _EQ014, GLOBAL( CLKI),  VCC,  VCC,  VCC);
  _EQ014 = !_LC5_A34 & !_LC5_A38 &  Q13
         #  _LC5_A34 & !_LC5_A38 & !Q13;

-- Node name is ':77' = 'Q14' 
-- Equation name is 'Q14', location is LC7_A34, type is buried.
Q14      = DFFE( _EQ015, GLOBAL( CLKI),  VCC,  VCC,  VCC);
  _EQ015 = !_LC5_A38 & !Q13 &  Q14
         # !_LC5_A34 & !_LC5_A38 &  Q14
         #  _LC5_A34 & !_LC5_A38 &  Q13 & !Q14;

-- Node name is ':76' = 'Q15' 
-- Equation name is 'Q15', location is LC5_A30, type is buried.
Q15      = DFFE( _EQ016, GLOBAL( CLKI),  VCC,  VCC,  VCC);
  _EQ016 = !_LC2_A34 & !_LC5_A38 &  Q15
         #  _LC2_A34 & !_LC5_A38 & !Q15;

-- Node name is ':75' = 'Q16' 
-- Equation name is 'Q16', location is LC1_A30, type is buried.
Q16      = DFFE( _EQ017, GLOBAL( CLKI),  VCC,  VCC,  VCC);
  _EQ017 = !_LC5_A38 & !Q15 &  Q16
         # !_LC2_A34 & !_LC5_A38 &  Q16
         #  _LC2_A34 & !_LC5_A38 &  Q15 & !Q16;

-- Node name is ':74' = 'Q17' 
-- Equation name is 'Q17', location is LC4_A30, type is buried.
Q17      = DFFE( _EQ018, GLOBAL( CLKI),  VCC,  VCC,  VCC);
  _EQ018 = !_LC3_A30 & !_LC5_A38 &  Q17
         #  _LC3_A30 & !_LC5_A38 & !Q17;

-- Node name is ':73' = 'Q18' 
-- Equation name is 'Q18', location is LC6_A30, type is buried.
Q18      = DFFE( _EQ019, GLOBAL( CLKI),  VCC,  VCC,  VCC);
  _EQ019 = !_LC5_A38 & !Q17 &  Q18
         # !_LC3_A30 & !_LC5_A38 &  Q18
         #  _LC3_A30 & !_LC5_A38 &  Q17 & !Q18;

-- Node name is ':72' = 'Q19' 
-- Equation name is 'Q19', location is LC8_A30, type is buried.
Q19      = DFFE( _EQ020, GLOBAL( CLKI),  VCC,  VCC,  VCC);
  _EQ020 = !_LC5_A38 & !Q18 &  Q19
         # !_LC5_A38 & !_LC7_A30 &  Q19
         # !_LC5_A38 &  _LC7_A30 &  Q18 & !Q19;

-- Node name is 'sel0' 
-- Equation name is 'sel0', type is output 
sel0     =  Q8;

-- Node name is 'sel1' 
-- Equation name is 'sel1', type is output 
sel1     =  Q9;

-- Node name is '|lpm_add_sub:179|addcore:adder|:119' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_A38', type is buried 
_LC3_A38 = LCELL( _EQ021);
  _EQ021 =  Q0 &  Q1;

-- Node name is '|lpm_add_sub:179|addcore:adder|:127' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_A38', type is buried 
_LC1_A38 = LCELL( _EQ022);
  _EQ022 =  Q0 &  Q1 &  Q2 &  Q3;

-- Node name is '|lpm_add_sub:179|addcore:adder|:131' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_A28', type is buried 
_LC7_A28 = LCELL( _EQ023);
  _EQ023 =  _LC1_A38 &  Q4;

-- Node name is '|lpm_add_sub:179|addcore:adder|:139' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_A36', type is buried 
_LC3_A36 = LCELL( _EQ024);
  _EQ024 =  _LC1_A38 &  Q4 &  Q5 &  Q6;

-- Node name is '|lpm_add_sub:179|addcore:adder|:143' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_A36', type is buried 
_LC5_A36 = LCELL( _EQ025);
  _EQ025 =  _LC3_A36 &  Q7;

-- Node name is '|lpm_add_sub:179|addcore:adder|:151' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_A36', type is buried 
_LC7_A36 = LCELL( _EQ026);
  _EQ026 =  _LC5_A36 &  Q8 &  Q9;

-- Node name is '|lpm_add_sub:179|addcore:adder|:155' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_A36', type is buried 
_LC8_A36 = LCELL( _EQ027);
  _EQ027 =  _LC5_A36 &  Q8 &  Q9 &  Q10;

-- Node name is '|lpm_add_sub:179|addcore:adder|:163' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_A34', type is buried 
_LC5_A34 = LCELL( _EQ028);
  _EQ028 =  _LC8_A36 &  Q11 &  Q12;

-- Node name is '|lpm_add_sub:179|addcore:adder|:171' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_A34', type is buried 
_LC2_A34 = LCELL( _EQ029);
  _EQ029 =  _LC5_A34 &  Q13 &  Q14;

-- Node name is '|lpm_add_sub:179|addcore:adder|:179' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_A30', type is buried 
_LC3_A30 = LCELL( _EQ030);
  _EQ030 =  _LC2_A34 &  Q15 &  Q16;

-- Node name is '|lpm_add_sub:179|addcore:adder|:183' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_A30', type is buried 
_LC7_A30 = LCELL( _EQ031);
  _EQ031 =  _LC3_A30 &  Q17;

-- Node name is '~5~1' 
-- Equation name is '~5~1', location is LC3_A34, type is buried.
-- synthesized logic cell 
_LC3_A34 = LCELL( _EQ032);
  _EQ032 = !Q13
         #  Q14
         #  Q15;

-- Node name is '~5~2' 
-- Equation name is '~5~2', location is LC4_A34, type is buried.
-- synthesized logic cell 
_LC4_A34 = LCELL( _EQ033);
  _EQ033 =  Q9
         # !Q10
         #  Q11;

-- Node name is '~5~3' 
-- Equation name is '~5~3', location is LC2_A30, type is buried.
-- synthesized logic cell 
_LC2_A30 = LCELL( _EQ034);
  _EQ034 =  Q16
         #  Q17
         # !Q18
         # !Q19;

-- Node name is '~5~4' 
-- Equation name is '~5~4', location is LC1_A34, type is buried.
-- synthesized logic cell 
_LC1_A34 = LCELL( _EQ035);
  _EQ035 = !Q12
         #  _LC3_A34
         #  _LC4_A34
         #  _LC2_A30;

-- Node name is '~5~5' 
-- Equation name is '~5~5', location is LC4_A28, type is buried.
-- synthesized logic cell 
_LC4_A28 = LCELL( _EQ036);
  _EQ036 =  Q5
         #  Q6
         #  Q0
         #  Q1;

-- Node name is '~5~6' 
-- Equation name is '~5~6', location is LC2_A38, type is buried.
-- synthesized logic cell 
_LC2_A38 = LCELL( _EQ037);
  _EQ037 =  Q2
         #  Q3
         #  Q4
         #  Q7;

-- Node name is ':5' 
-- Equation name is '_LC5_A38', type is buried 
!_LC5_A38 = _LC5_A38~NOT;
_LC5_A38~NOT = LCELL( _EQ038);
  _EQ038 = !Q8
         #  _LC1_A34
         #  _LC4_A28
         #  _LC2_A38;

-- Node name is '~172~1' 
-- Equation name is '~172~1', location is LC5_A28, type is buried.
-- synthesized logic cell 
_LC5_A28 = LCELL( _EQ039);
  _EQ039 =  Q4 &  Q5 &  Q6 &  Q7;

-- Node name is '~172~2' 
-- Equation name is '~172~2', location is LC8_A38, type is buried.
-- synthesized logic cell 
_LC8_A38 = LCELL( _EQ040);
  _EQ040 =  _LC5_A28 &  Q2 &  Q3 & !Q8;

-- Node name is ':172' 
-- Equation name is '_LC6_A38', type is buried 
_LC6_A38 = LCELL( _EQ041);
  _EQ041 = !_LC1_A34 &  _LC8_A38 &  Q0
         # !_LC1_A34 &  _LC8_A38 &  Q1;



Project Information                               c:\maxplus2\verilog6\div.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:10
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:03
   --------------------------             --------
   Total Time                             00:00:14


Memory Allocated
-----------------

Peak memory allocated during compilation  = 50,072K

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